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| author | Jack Xu <jack.xu@intel.com> | 2020-11-06 19:27:50 +0800 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2020-11-13 20:38:50 +1100 |
| commit | 8f87b6271ec85c09af6406665324c74bb79e3216 (patch) | |
| tree | 0173c12cc4d0462321cf483ab7c6308a78d6db13 /drivers/crypto/qat/qat_common/qat_hal.c | |
| parent | 10fb050caef99d75895bf0978188090d3ed676c2 (diff) | |
| download | linux-8f87b6271ec85c09af6406665324c74bb79e3216.tar.gz linux-8f87b6271ec85c09af6406665324c74bb79e3216.tar.bz2 linux-8f87b6271ec85c09af6406665324c74bb79e3216.zip | |
crypto: qat - remove global CSRs helpers
Include the offset of GLOBAL_CSR directly into the enum hal_global_csr
and remove the macros SET_GLB_CSR/GET_GLB_CSR to simplify the global CSR
access.
Signed-off-by: Jack Xu <jack.xu@intel.com>
Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/qat/qat_common/qat_hal.c')
| -rw-r--r-- | drivers/crypto/qat/qat_common/qat_hal.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c index f127233eec17..15ebb57ea14a 100644 --- a/drivers/crypto/qat/qat_common/qat_hal.c +++ b/drivers/crypto/qat/qat_common/qat_hal.c @@ -273,10 +273,10 @@ void qat_hal_reset(struct icp_qat_fw_loader_handle *handle) { unsigned int ae_reset_csr; - ae_reset_csr = GET_GLB_CSR(handle, ICP_RESET); + ae_reset_csr = GET_CAP_CSR(handle, ICP_RESET); ae_reset_csr |= handle->hal_handle->ae_mask << RST_CSR_AE_LSB; ae_reset_csr |= handle->hal_handle->slice_mask << RST_CSR_QAT_LSB; - SET_GLB_CSR(handle, ICP_RESET, ae_reset_csr); + SET_CAP_CSR(handle, ICP_RESET, ae_reset_csr); } static void qat_hal_wr_indr_csr(struct icp_qat_fw_loader_handle *handle, @@ -390,9 +390,9 @@ static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle) unsigned char ae; /* stop the timestamp timers */ - misc_ctl = GET_GLB_CSR(handle, MISC_CONTROL); + misc_ctl = GET_CAP_CSR(handle, MISC_CONTROL); if (misc_ctl & MC_TIMESTAMP_ENABLE) - SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl & + SET_CAP_CSR(handle, MISC_CONTROL, misc_ctl & (~MC_TIMESTAMP_ENABLE)); for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { @@ -400,7 +400,7 @@ static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle) qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0); } /* start timestamp timers */ - SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl | MC_TIMESTAMP_ENABLE); + SET_CAP_CSR(handle, MISC_CONTROL, misc_ctl | MC_TIMESTAMP_ENABLE); } #define ESRAM_AUTO_TINIT BIT(2) @@ -448,21 +448,21 @@ int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle) unsigned int csr; /* write to the reset csr */ - ae_reset_csr = GET_GLB_CSR(handle, ICP_RESET); + ae_reset_csr = GET_CAP_CSR(handle, ICP_RESET); ae_reset_csr &= ~(handle->hal_handle->ae_mask << RST_CSR_AE_LSB); ae_reset_csr &= ~(handle->hal_handle->slice_mask << RST_CSR_QAT_LSB); do { - SET_GLB_CSR(handle, ICP_RESET, ae_reset_csr); + SET_CAP_CSR(handle, ICP_RESET, ae_reset_csr); if (!(times--)) goto out_err; - csr = GET_GLB_CSR(handle, ICP_RESET); + csr = GET_CAP_CSR(handle, ICP_RESET); } while ((handle->hal_handle->ae_mask | (handle->hal_handle->slice_mask << RST_CSR_QAT_LSB)) & csr); /* enable clock */ - clk_csr = GET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE); + clk_csr = GET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE); clk_csr |= handle->hal_handle->ae_mask << 0; clk_csr |= handle->hal_handle->slice_mask << 20; - SET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr); + SET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr); if (qat_hal_check_ae_alive(handle)) goto out_err; |