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authorBen Widawsky <ben.widawsky@intel.com>2021-05-20 14:29:53 -0700
committerDan Williams <dan.j.williams@intel.com>2021-05-26 11:20:18 -0700
commit6630d31c912ed2dfbc035caf0f54709b50ce779e (patch)
treecf3a5652ccf2e201dbc0f49194c70111262a4d33 /drivers/cxl
parent1d5a4159074bde1b2d5e4a6f5ed34de70a83a39f (diff)
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cxl/mem: Get rid of @cxlm.base
@cxlm.base only existed to support holding the base found in the register block mapping code, and pass it along to the register setup code. Now that the register setup function has all logic around managing the registers, from DVSEC to iomapping up to populating our CXL specific information, it is easy to turn the @base values into local variables and remove them from our device driver state. Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Link: https://lore.kernel.org/r/20210520212953.1181695-1-ben.widawsky@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl')
-rw-r--r--drivers/cxl/mem.h2
-rw-r--r--drivers/cxl/pci.c24
2 files changed, 11 insertions, 15 deletions
diff --git a/drivers/cxl/mem.h b/drivers/cxl/mem.h
index 23fc40dde27e..13868ff7cadf 100644
--- a/drivers/cxl/mem.h
+++ b/drivers/cxl/mem.h
@@ -49,7 +49,6 @@ struct cxl_memdev {
/**
* struct cxl_mem - A CXL memory device
* @pdev: The PCI device associated with this CXL device.
- * @base: IO mappings to the device's MMIO
* @cxlmd: Logical memory device chardev / interface
* @regs: Parsed register blocks
* @payload_size: Size of space for payload
@@ -64,7 +63,6 @@ struct cxl_memdev {
*/
struct cxl_mem {
struct pci_dev *pdev;
- void __iomem *base;
struct cxl_memdev *cxlmd;
struct cxl_regs regs;
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index df6ccdcceea5..8bdae74d7d78 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -922,11 +922,10 @@ static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev)
return cxlm;
}
-static int cxl_mem_map_regblock(struct cxl_mem *cxlm, u32 reg_lo, u32 reg_hi)
+static void __iomem *cxl_mem_map_regblock(struct cxl_mem *cxlm, u32 reg_lo, u32 reg_hi)
{
struct pci_dev *pdev = cxlm->pdev;
struct device *dev = &pdev->dev;
- void __iomem *regs;
u64 offset;
u8 bar;
int rc;
@@ -938,20 +937,18 @@ static int cxl_mem_map_regblock(struct cxl_mem *cxlm, u32 reg_lo, u32 reg_hi)
if (pci_resource_len(pdev, bar) < offset) {
dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar,
&pdev->resource[bar], (unsigned long long)offset);
- return -ENXIO;
+ return IOMEM_ERR_PTR(-ENXIO);
}
rc = pcim_iomap_regions(pdev, BIT(bar), pci_name(pdev));
if (rc) {
dev_err(dev, "failed to map registers\n");
- return rc;
+ return IOMEM_ERR_PTR(rc);
}
- regs = pcim_iomap_table(pdev)[bar];
-
- cxlm->base = regs + offset;
dev_dbg(dev, "Mapped CXL Memory Device resource\n");
- return 0;
+
+ return pcim_iomap_table(pdev)[bar] + offset;
}
static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec)
@@ -993,7 +990,8 @@ static int cxl_mem_setup_regs(struct cxl_mem *cxlm)
struct pci_dev *pdev = cxlm->pdev;
struct device *dev = &pdev->dev;
u32 regloc_size, regblocks;
- int rc, regloc, i;
+ void __iomem *base;
+ int regloc, i;
regloc = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_CXL_REGLOC_OFFSET);
if (!regloc) {
@@ -1019,9 +1017,9 @@ static int cxl_mem_setup_regs(struct cxl_mem *cxlm)
reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo);
if (reg_type == CXL_REGLOC_RBI_MEMDEV) {
- rc = cxl_mem_map_regblock(cxlm, reg_lo, reg_hi);
- if (rc)
- return rc;
+ base = cxl_mem_map_regblock(cxlm, reg_lo, reg_hi);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
break;
}
}
@@ -1031,7 +1029,7 @@ static int cxl_mem_setup_regs(struct cxl_mem *cxlm)
return -ENXIO;
}
- cxl_setup_device_regs(dev, cxlm->base, &regs->device_regs);
+ cxl_setup_device_regs(dev, base, &regs->device_regs);
if (!regs->status || !regs->mbox || !regs->memdev) {
dev_err(dev, "registers not found: %s%s%s\n",