diff options
| author | Narayanan G <narayanan.gopalakrishnan@stericsson.com> | 2011-11-17 17:26:41 +0530 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@linux.intel.com> | 2011-11-22 09:46:06 +0530 |
| commit | 7fb3e75e1833743d5faf3adbae46b63f503c6fdf (patch) | |
| tree | 32ae4d6b39e5a552e9727ff15a891e4ba2b980fb /drivers/dma/ste_dma40_ll.h | |
| parent | ca21a146a45a179a2a7bc86d938a2fbf571a7510 (diff) | |
| download | linux-7fb3e75e1833743d5faf3adbae46b63f503c6fdf.tar.gz linux-7fb3e75e1833743d5faf3adbae46b63f503c6fdf.tar.bz2 linux-7fb3e75e1833743d5faf3adbae46b63f503c6fdf.zip | |
dmaengine/ste_dma40: support pm in dma40
This patch adds power management support to the dma40
driver. The DMA registers are backed up and restored,
during suspend/resume. Also flags to track the dma usage
have been introduced to facilitate this. Patch also includes
few other minor changes, related to formatting, comments.
Signed-off-by: Narayanan G <narayanan.gopalakrishnan@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Diffstat (limited to 'drivers/dma/ste_dma40_ll.h')
| -rw-r--r-- | drivers/dma/ste_dma40_ll.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h index b44c455158de..8d3d490968a3 100644 --- a/drivers/dma/ste_dma40_ll.h +++ b/drivers/dma/ste_dma40_ll.h @@ -16,6 +16,8 @@ #define D40_TYPE_TO_GROUP(type) (type / 16) #define D40_TYPE_TO_EVENT(type) (type % 16) +#define D40_GROUP_SIZE 8 +#define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2) /* Most bits of the CFG register are the same in log as in phy mode */ #define D40_SREG_CFG_MST_POS 15 @@ -123,6 +125,15 @@ /* DMA Register Offsets */ #define D40_DREG_GCC 0x000 +#define D40_DREG_GCC_ENA 0x1 +/* This assumes that there are only 4 event groups */ +#define D40_DREG_GCC_ENABLE_ALL 0xff01 +#define D40_DREG_GCC_EVTGRP_POS 8 +#define D40_DREG_GCC_SRC 0 +#define D40_DREG_GCC_DST 1 +#define D40_DREG_GCC_EVTGRP_ENA(x, y) \ + (1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y)) + #define D40_DREG_PRTYP 0x004 #define D40_DREG_PRSME 0x008 #define D40_DREG_PRSMO 0x00C |