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authorBorislav Petkov <borislav.petkov@amd.com>2010-03-08 18:29:35 +0100
committerBorislav Petkov <borislav.petkov@amd.com>2010-08-03 16:14:04 +0200
commit9975a5f22a4fcc8d08035c65439900a983f891ad (patch)
tree33fbd72a4f4bc1d7097e46db6bf46a4848d7f74b /drivers/edac
parentf4347553b30ec66530bfe63c84530afea3803396 (diff)
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amd64_edac: Fix DCT base address selector
The correct check is to verify whether in high range we're below 4GB and not to extract the DctSelBaseAddr again. See "2.8.5 Routing DRAM Requests" in the F10h BKDG. Cc: <stable@kernel.org> # .32.x .33.x .34.x Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Acked-by: Doug Thompson <dougthompson@xmission.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/amd64_edac.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index a44e90abb755..4129aa0930cd 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1435,7 +1435,7 @@ static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel,
u64 chan_off;
if (hi_range_sel) {
- if (!(dct_sel_base_addr & 0xFFFFF800) &&
+ if (!(dct_sel_base_addr & 0xFFFF0000) &&
hole_valid && (sys_addr >= 0x100000000ULL))
chan_off = hole_off << 16;
else