summaryrefslogtreecommitdiffstats
path: root/drivers/edac
diff options
context:
space:
mode:
authorYork Sun <york.sun@nxp.com>2016-08-09 14:55:42 -0700
committerBorislav Petkov <bp@suse.de>2016-09-01 10:28:01 +0200
commit4e2c3252d2426cd05286e38650365f215571d3c6 (patch)
tree964296a048b48ed1ad2c5f594ea5408114828068 /drivers/edac
parentd43a9fb202bc86a6f5a2bb44b06cf9fd5581080b (diff)
downloadlinux-4e2c3252d2426cd05286e38650365f215571d3c6.tar.gz
linux-4e2c3252d2426cd05286e38650365f215571d3c6.tar.bz2
linux-4e2c3252d2426cd05286e38650365f215571d3c6.zip
EDAC, fsl_ddr: Add missing DDR DRAM types
The compatible DDR controllers may support DDR, DDR2, DDR3, DDR4 DRAM. An individual controller doesn't support all of them. The EDAC driver reads SDRAM_CFG to determine which mode is configured. Add DDR4 and drop the defines used only in the mtype assignment. Signed-off-by: York Sun <york.sun@nxp.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: morbidrsa@gmail.com Cc: oss@buserror.net Cc: stuart.yoder@nxp.com Link: http://lkml.kernel.org/r/1470779760-16483-6-git-send-email-york.sun@nxp.com Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/fsl_ddr_edac.c24
-rw-r--r--drivers/edac/fsl_ddr_edac.h4
2 files changed, 16 insertions, 12 deletions
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index 26758337e23e..46b00e15e442 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -371,30 +371,36 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
sdtype = sdram_ctl & DSC_SDTYPE_MASK;
if (sdram_ctl & DSC_RD_EN) {
switch (sdtype) {
- case DSC_SDTYPE_DDR:
+ case 0x02000000:
mtype = MEM_RDDR;
break;
- case DSC_SDTYPE_DDR2:
+ case 0x03000000:
mtype = MEM_RDDR2;
break;
- case DSC_SDTYPE_DDR3:
+ case 0x07000000:
mtype = MEM_RDDR3;
break;
+ case 0x05000000:
+ mtype = MEM_RDDR4;
+ break;
default:
mtype = MEM_UNKNOWN;
break;
}
} else {
switch (sdtype) {
- case DSC_SDTYPE_DDR:
+ case 0x02000000:
mtype = MEM_DDR;
break;
- case DSC_SDTYPE_DDR2:
+ case 0x03000000:
mtype = MEM_DDR2;
break;
- case DSC_SDTYPE_DDR3:
+ case 0x07000000:
mtype = MEM_DDR3;
break;
+ case 0x05000000:
+ mtype = MEM_DDR4;
+ break;
default:
mtype = MEM_UNKNOWN;
break;
@@ -499,8 +505,10 @@ int fsl_mc_err_probe(struct platform_device *op)
}
edac_dbg(3, "init mci\n");
- mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
- MEM_FLAG_DDR | MEM_FLAG_DDR2;
+ mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR |
+ MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 |
+ MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 |
+ MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
mci->edac_cap = EDAC_FLAG_SECDED;
mci->mod_name = EDAC_MOD_STR;
diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h
index 1eccc62b5d93..4ccee292eff1 100644
--- a/drivers/edac/fsl_ddr_edac.h
+++ b/drivers/edac/fsl_ddr_edac.h
@@ -50,10 +50,6 @@
#define DSC_DBW_64 0x00000000
#define DSC_SDTYPE_MASK 0x07000000
-
-#define DSC_SDTYPE_DDR 0x02000000
-#define DSC_SDTYPE_DDR2 0x03000000
-#define DSC_SDTYPE_DDR3 0x07000000
#define DSC_X32_EN 0x00000020
/* Err_Int_En */