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| author | Yazen Ghannam <yazen.ghannam@amd.com> | 2019-02-12 21:24:29 +0000 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2019-02-15 14:36:31 +0100 |
| commit | a0bcd3c0b8a52ba0eb74371fa6be15ad0390ba67 (patch) | |
| tree | 380789256dfb507b419ed0bddbcc38e791715219 /drivers/edac | |
| parent | 3f4da372ec8e4ce58c17ac4f2e3c8891bbfea17e (diff) | |
| download | linux-a0bcd3c0b8a52ba0eb74371fa6be15ad0390ba67.tar.gz linux-a0bcd3c0b8a52ba0eb74371fa6be15ad0390ba67.tar.bz2 linux-a0bcd3c0b8a52ba0eb74371fa6be15ad0390ba67.zip | |
EDAC/mce_amd: Decode MCA_STATUS in bit definition order
Sort the MCA_STATUS bits in decode output to follow how they are defined
in the register.
The order is as follows:
Bit | Decode
------------
62 | Over
61 | UC
59 | MiscV
58 | AddrV
57 | PCC
55 | TCC
53 | SyndV
46 | CECC
45 | UECC
44 | Deferred
43 | Poison
40 | Scrub
[ bp: Massage a bit. ]
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86@kernel.org
Link: https://lkml.kernel.org/r/20190212212417.107049-2-Yazen.Ghannam@amd.com
Diffstat (limited to 'drivers/edac')
| -rw-r--r-- | drivers/edac/mce_amd.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index b349c22bb386..0a1814dad6cf 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1051,26 +1051,18 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) ((m->status & MCI_STATUS_UC) ? "UE" : (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"), ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"), - ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"), - ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-")); - - if (fam >= 0x15) { - pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-")); - - /* F15h, bank4, bit 43 is part of McaStatSubCache. */ - if (fam != 0x15 || m->bank != 4) - pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-")); - } + ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"), + ((m->status & MCI_STATUS_PCC) ? "PCC" : "-")); if (boot_cpu_has(X86_FEATURE_SMCA)) { u32 low, high; u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); - pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-")); - if (!rdmsr_safe(addr, &low, &high) && (low & MCI_CONFIG_MCAX)) pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-")); + + pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-")); } /* do the two bits[14:13] together */ @@ -1078,6 +1070,14 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) if (ecc) pr_cont("|%sECC", ((ecc == 2) ? "C" : "U")); + if (fam >= 0x15) { + pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-")); + + /* F15h, bank4, bit 43 is part of McaStatSubCache. */ + if (fam != 0x15 || m->bank != 4) + pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-")); + } + if (fam >= 0x17) pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-")); |