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| author | Olof Johansson <olof@lixom.net> | 2017-01-29 16:08:07 -0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2017-01-29 16:08:07 -0800 |
| commit | 1ae777618948ef6be566a8f993fce0638e08fc99 (patch) | |
| tree | 80062db7f77f70dcaa65d9951e5a2f7ffd0d5698 /drivers/firmware | |
| parent | 5f1223c5b09262bb5c88f77d2938c9a5ffefa40c (diff) | |
| parent | a811b420b6c13759540070c0e9541b7cd8569168 (diff) | |
| download | linux-1ae777618948ef6be566a8f993fce0638e08fc99.tar.gz linux-1ae777618948ef6be566a8f993fce0638e08fc99.tar.bz2 linux-1ae777618948ef6be566a8f993fce0638e08fc99.zip | |
Merge tag 'qcom-drivers-for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers
Qualcomm ARM Based Driver Updates for v4.11
* Fix issues with SCM compile testing
* Add SCM set remote state API
* Mask APQ8064 SCM clock dependency issue
* Add Qualcomm DMA folder to MAINTAINERS
* Fix EBI2 dependencies
* tag 'qcom-drivers-for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
firmware: qcom_scm: Add set remote state API
MAINTAINERS: Update the files to include the Qualcomm DMA folder
bus: qcom_ebi2: default y if ARCH_QCOM
firmware: qcom: scm: Mask APQ8064 core clk dependency
firmware: qcom: scm: Add empty functions to help compile testing
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/firmware')
| -rw-r--r-- | drivers/firmware/qcom_scm-32.c | 18 | ||||
| -rw-r--r-- | drivers/firmware/qcom_scm-64.c | 16 | ||||
| -rw-r--r-- | drivers/firmware/qcom_scm.c | 8 | ||||
| -rw-r--r-- | drivers/firmware/qcom_scm.h | 2 |
4 files changed, 43 insertions, 1 deletions
diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index c6aeedbdcbb0..8ad226c60374 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -560,3 +560,21 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) return ret ? : le32_to_cpu(out); } + +int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) +{ + struct { + __le32 state; + __le32 id; + } req; + __le32 scm_ret = 0; + int ret; + + req.state = cpu_to_le32(state); + req.id = cpu_to_le32(id); + + ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE, + &req, sizeof(req), &scm_ret, sizeof(scm_ret)); + + return ret ? : le32_to_cpu(scm_ret); +} diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 4a0f5ead4fb5..4b220abaf363 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -358,3 +358,19 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) return ret ? : res.a1; } + +int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) +{ + struct qcom_scm_desc desc = {0}; + struct arm_smccc_res res; + int ret; + + desc.args[0] = state; + desc.args[1] = id; + desc.arginfo = QCOM_SCM_ARGS(2); + + ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE, + &desc, &res); + + return ret ? : res.a1; +} diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 893f953eaccf..d987bcc7489d 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -324,6 +324,12 @@ bool qcom_scm_is_available(void) } EXPORT_SYMBOL(qcom_scm_is_available); +int qcom_scm_set_remote_state(u32 state, u32 id) +{ + return __qcom_scm_set_remote_state(__scm->dev, state, id); +} +EXPORT_SYMBOL(qcom_scm_set_remote_state); + static int qcom_scm_probe(struct platform_device *pdev) { struct qcom_scm *scm; @@ -387,7 +393,7 @@ static int qcom_scm_probe(struct platform_device *pdev) static const struct of_device_id qcom_scm_dt_match[] = { { .compatible = "qcom,scm-apq8064", - .data = (void *) SCM_HAS_CORE_CLK, + /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */ }, { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK, diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 3584b00fe7e6..6a0f15469344 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -15,6 +15,8 @@ #define QCOM_SCM_SVC_BOOT 0x1 #define QCOM_SCM_BOOT_ADDR 0x1 #define QCOM_SCM_BOOT_ADDR_MC 0x11 +#define QCOM_SCM_SET_REMOTE_STATE 0xa +extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id); #define QCOM_SCM_FLAG_HLOS 0x01 #define QCOM_SCM_FLAG_COLDBOOT_MC 0x02 |