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author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-03 11:44:24 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-03 11:44:24 -0700 |
commit | 2f34c1231bfc9f2550f934acb268ac7315fb3837 (patch) | |
tree | ff8114b3b4ec4723a11b041c6b74c389e9f0eeb9 /drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h | |
parent | a3719f34fdb664ffcfaec2160ef20fca7becf2ee (diff) | |
parent | 8b03d1ed2c43a2ba5ef3381322ee4515b97381bf (diff) | |
download | linux-2f34c1231bfc9f2550f934acb268ac7315fb3837.tar.gz linux-2f34c1231bfc9f2550f934acb268ac7315fb3837.tar.bz2 linux-2f34c1231bfc9f2550f934acb268ac7315fb3837.zip |
Merge tag 'drm-for-v4.12' of git://people.freedesktop.org/~airlied/linux
Pull drm u pdates from Dave Airlie:
"This is the main drm pull request for v4.12. Apart from two fixes
pulls, everything should have been in drm-next for at least 2 weeks.
The biggest thing in here is AMD released the public headers for their
upcoming VEGA GPUs. These as always are quite a sizeable chunk of
header files. They've also added initial non-display support for those
GPUs, though they aren't available in production yet.
Otherwise it's pretty much normal.
New bridge drivers:
- megachips-stdpxxxx-ge-b850v3-fw LVDS->DP++
- generic LVDS bridge support.
Core:
- Displayport link train failure reporting to userspace
- debugfs interface cleaned up
- subsystem TODO in kerneldoc now
- Extended fbdev support (flipping and vblank wait)
- drm_platform removed
- EDP CRC support in helper
- HF-VSDB SCDC support in EDID parser
- Lots of code cleanups and header extraction
- Thunderbolt external GPU awareness
- Atomic helper improvements
- Documentation improvements
panel:
- Sitronix and Samsung new panel support
amdgpu:
- Preliminary vega10 support
- Multi-level page table support
- GPU sensor support for userspace
- PRT support for sparse buffers
- SR-IOV improvements
- Non-contig VRAM CPU mapping
i915:
- Atomic modesetting enabled by default on Gen5+
- LSPCON improvements
- Atomic state handling for cdclk
- GPU reset improvements
- In-kernel unit tests
- Geminilake improvements and color manager support
- Designware i2c fixes
- vblank evasion improvements
- Hotplug safe connector iterators
- GVT scheduler QoS support
- GVT Kabylake support
nouveau:
- Acceleration support for Pascal (GP10x).
- Rearchitecture of code handling proprietary signed firmware
- Fix GTX 970 with odd MMU configuration
- GP10B support
- GP107 acceleration support
vmwgfx:
- Atomic modesetting support for vmwgfx
omapdrm:
- Support for render nodes
- Refactor omapdss code
- Fix some probe ordering issues
- Fix too dark RGB565 rendering
sunxi:
- prelim rework for multiple pipes.
mali-dp:
- Color management support
- Plane scaling
- Power management improvements
imx-drm:
- Prefetch Resolve Engine/Gasket on i.MX6QP
- Deferred plane disabling
- Separate alpha support
mediatek:
- Mediatek SoC MT2701 support
rcar-du:
- Gen3 HDMI support
msm:
- 4k support for newer chips
- OPP bindings for gpu
- prep work for per-process pagetables
vc4:
- HDMI audio support
- fixes
qxl:
- minor fixes.
dw-hdmi:
- PHY improvements
- CSC fixes
- Amlogic GX SoC support"
* tag 'drm-for-v4.12' of git://people.freedesktop.org/~airlied/linux: (1778 commits)
drm/nouveau/fb/gf100-: Fix 32 bit wraparound in new ram detection
drm/nouveau/secboot/gm20b: fix the error return code in gm20b_secboot_tegra_read_wpr()
drm/nouveau/kms: Increase max retries in scanout position queries.
drm/nouveau/bios/bitP: check that table is long enough for optional pointers
drm/nouveau/fifo/nv40: no ctxsw for pre-nv44 mpeg engine
drm: mali-dp: use div_u64 for expensive 64-bit divisions
drm/i915: Confirm the request is still active before adding it to the await
drm/i915: Avoid busy-spinning on VLV_GLTC_PW_STATUS mmio
drm/i915/selftests: Allocate inode/file dynamically
drm/i915: Fix system hang with EI UP masked on Haswell
drm/i915: checking for NULL instead of IS_ERR() in mock selftests
drm/i915: Perform link quality check unconditionally during long pulse
drm/i915: Fix use after free in lpe_audio_platdev_destroy()
drm/i915: Use the right mapping_gfp_mask for final shmem allocation
drm/i915: Make legacy cursor updates more unsynced
drm/i915: Apply a cond_resched() to the saturated signaler
drm/i915: Park the signaler before sleeping
drm: mali-dp: Check the mclk rate and allow up/down scaling
drm: mali-dp: Enable image enhancement when scaling
drm: mali-dp: Add plane upscaling support
...
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h')
-rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h | 1271 |
1 files changed, 1271 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h new file mode 100644 index 000000000000..daa7eaef01b8 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h @@ -0,0 +1,1271 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _nbif_6_1_DEFAULT_HEADER +#define _nbif_6_1_DEFAULT_HEADER + + +// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x0 +#define cfgVENDOR_ID_DEFAULT 0x00000000 +#define cfgDEVICE_ID_DEFAULT 0x00000000 +#define cfgCOMMAND_DEFAULT 0x00000000 +#define cfgSTATUS_DEFAULT 0x00000000 +#define cfgREVISION_ID_DEFAULT 0x00000000 +#define cfgPROG_INTERFACE_DEFAULT 0x00000000 +#define cfgSUB_CLASS_DEFAULT 0x00000000 +#define cfgBASE_CLASS_DEFAULT 0x00000000 +#define cfgCACHE_LINE_DEFAULT 0x00000000 +#define cfgLATENCY_DEFAULT 0x00000000 +#define cfgHEADER_DEFAULT 0x00000000 +#define cfgBIST_DEFAULT 0x00000000 +#define cfgBASE_ADDR_1_DEFAULT 0x00000000 +#define cfgBASE_ADDR_2_DEFAULT 0x00000000 +#define cfgBASE_ADDR_3_DEFAULT 0x00000000 +#define cfgBASE_ADDR_4_DEFAULT 0x00000000 +#define cfgBASE_ADDR_5_DEFAULT 0x00000000 +#define cfgBASE_ADDR_6_DEFAULT 0x00000000 +#define cfgADAPTER_ID_DEFAULT 0x00000000 +#define cfgROM_BASE_ADDR_DEFAULT 0x00000000 +#define cfgCAP_PTR_DEFAULT 0x00000000 +#define cfgINTERRUPT_LINE_DEFAULT 0x000000ff +#define cfgINTERRUPT_PIN_DEFAULT 0x00000000 +#define cfgMIN_GRANT_DEFAULT 0x00000000 +#define cfgMAX_LATENCY_DEFAULT 0x00000000 +#define cfgVENDOR_CAP_LIST_DEFAULT 0x00000000 +#define cfgADAPTER_ID_W_DEFAULT 0x00000000 +#define cfgPMI_CAP_LIST_DEFAULT 0x00000000 +#define cfgPMI_CAP_DEFAULT 0x00000000 +#define cfgPMI_STATUS_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_CAP_LIST_DEFAULT 0x0000a000 +#define cfgPCIE_CAP_DEFAULT 0x00000002 +#define cfgDEVICE_CAP_DEFAULT 0x10000000 +#define cfgDEVICE_CNTL_DEFAULT 0x00002810 +#define cfgDEVICE_STATUS_DEFAULT 0x00000000 +#define cfgLINK_CAP_DEFAULT 0x00011c03 +#define cfgLINK_CNTL_DEFAULT 0x00000000 +#define cfgLINK_STATUS_DEFAULT 0x00000001 +#define cfgDEVICE_CAP2_DEFAULT 0x00000000 +#define cfgDEVICE_CNTL2_DEFAULT 0x00000000 +#define cfgDEVICE_STATUS2_DEFAULT 0x00000000 +#define cfgLINK_CAP2_DEFAULT 0x0000000e +#define cfgLINK_CNTL2_DEFAULT 0x00000003 +#define cfgLINK_STATUS2_DEFAULT 0x00000000 +#define cfgSLOT_CAP2_DEFAULT 0x00000000 +#define cfgSLOT_CNTL2_DEFAULT 0x00000000 +#define cfgSLOT_STATUS2_DEFAULT 0x00000000 +#define cfgMSI_CAP_LIST_DEFAULT 0x0000c000 +#define cfgMSI_MSG_CNTL_DEFAULT 0x00000080 +#define cfgMSI_MSG_ADDR_LO_DEFAULT 0x00000000 +#define cfgMSI_MSG_ADDR_HI_DEFAULT 0x00000000 +#define cfgMSI_MSG_DATA_DEFAULT 0x00000000 +#define cfgMSI_MSG_DATA_64_DEFAULT 0x00000000 +#define cfgMSI_MASK_DEFAULT 0x00000000 +#define cfgMSI_PENDING_DEFAULT 0x00000000 +#define cfgMSI_MASK_64_DEFAULT 0x00000000 +#define cfgMSI_PENDING_64_DEFAULT 0x00000000 +#define cfgMSIX_CAP_LIST_DEFAULT 0x00000000 +#define cfgMSIX_MSG_CNTL_DEFAULT 0x00000000 +#define cfgMSIX_TABLE_DEFAULT 0x00000000 +#define cfgMSIX_PBA_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +#define cfgPCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +#define cfgPCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +#define cfgPCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +#define cfgPCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgPCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +#define cfgPCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgPCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +#define cfgPCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +#define cfgPCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +#define cfgPCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +#define cfgPCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +#define cfgPCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +#define cfgPCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +#define cfgPCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_HDR_LOG0_DEFAULT 0x00000000 +#define cfgPCIE_HDR_LOG1_DEFAULT 0x00000000 +#define cfgPCIE_HDR_LOG2_DEFAULT 0x00000000 +#define cfgPCIE_HDR_LOG3_DEFAULT 0x00000000 +#define cfgPCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +#define cfgPCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_ERR_SRC_ID_DEFAULT 0x00000000 +#define cfgPCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +#define cfgPCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +#define cfgPCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +#define cfgPCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +#define cfgPCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +#define cfgPCIE_BAR1_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR1_CNTL_DEFAULT 0x00000020 +#define cfgPCIE_BAR2_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR2_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_BAR3_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR3_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_BAR4_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR4_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_BAR5_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR5_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_BAR6_CAP_DEFAULT 0x00000000 +#define cfgPCIE_BAR6_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +#define cfgPCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +#define cfgPCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +#define cfgPCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +#define cfgPCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +#define cfgPCIE_DPA_CAP_DEFAULT 0x00000000 +#define cfgPCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +#define cfgPCIE_DPA_STATUS_DEFAULT 0x00000100 +#define cfgPCIE_DPA_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +#define cfgPCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 +#define cfgPCIE_LINK_CNTL3_DEFAULT 0x00000000 +#define cfgPCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +#define cfgPCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +#define cfgPCIE_ACS_CAP_DEFAULT 0x00000000 +#define cfgPCIE_ACS_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 +#define cfgPCIE_ATS_CAP_DEFAULT 0x00000000 +#define cfgPCIE_ATS_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 +#define cfgPCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 +#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 +#define cfgPCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 +#define cfgPCIE_PASID_CAP_DEFAULT 0x00000000 +#define cfgPCIE_PASID_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 +#define cfgPCIE_TPH_REQR_CAP_DEFAULT 0x00000000 +#define cfgPCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +#define cfgPCIE_MC_CAP_DEFAULT 0x00000000 +#define cfgPCIE_MC_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_MC_ADDR0_DEFAULT 0x00000000 +#define cfgPCIE_MC_ADDR1_DEFAULT 0x00000000 +#define cfgPCIE_MC_RCV0_DEFAULT 0x00000000 +#define cfgPCIE_MC_RCV1_DEFAULT 0x00000000 +#define cfgPCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +#define cfgPCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +#define cfgPCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 +#define cfgPCIE_LTR_CAP_DEFAULT 0x00000000 +#define cfgPCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +#define cfgPCIE_ARI_CAP_DEFAULT 0x00000000 +#define cfgPCIE_ARI_CNTL_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_CAP_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_CONTROL_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 +#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 + + +// addressBlock: bif_cfg_dev0_swds_bifcfgdecp +// base address: 0x0 +#define mmSUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define mmIO_BASE_LIMIT_DEFAULT 0x00000000 +#define mmSECONDARY_STATUS_DEFAULT 0x00000000 +#define mmMEM_BASE_LIMIT_DEFAULT 0x00000000 +#define mmPREF_BASE_LIMIT_DEFAULT 0x00000000 +#define mmPREF_BASE_UPPER_DEFAULT 0x00000000 +#define mmPREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define mmIO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define mmIRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define mmSLOT_CAP_DEFAULT 0x00000000 +#define mmSLOT_CNTL_DEFAULT 0x00000000 +#define mmSLOT_STATUS_DEFAULT 0x00000000 +#define mmSSID_CAP_LIST_DEFAULT 0x00000000 +#define mmSSID_CAP_DEFAULT 0x00000000 + + +// addressBlock: rcc_shadow_reg_shadowdec +// base address: 0x0 +#define ixSHADOW_COMMAND_DEFAULT 0x00000000 +#define ixSHADOW_BASE_ADDR_1_DEFAULT 0x00000000 +#define ixSHADOW_BASE_ADDR_2_DEFAULT 0x00000000 +#define ixSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +#define ixSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000 +#define ixSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000 +#define ixSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000 +#define ixSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000 +#define ixSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +#define ixSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +#define ixSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +#define ixSUC_INDEX_DEFAULT 0x00000000 +#define ixSUC_DATA_DEFAULT 0x00000000 + + +// addressBlock: bif_bx_pf_SUMDEC +// base address: 0x0 +#define ixSUM_INDEX_DEFAULT 0x00000000 +#define ixSUM_DATA_DEFAULT 0x00000000 + + +// addressBlock: gdc_GDCDEC +// base address: 0x1400000 +#define mmA2S_CNTL_CL0_DEFAULT 0x00280540 +#define mmA2S_CNTL_CL1_DEFAULT 0x00282540 +#define mmA2S_CNTL_CL2_DEFAULT 0x002825a0 +#define mmA2S_CNTL_CL3_DEFAULT 0x00282550 +#define mmA2S_CNTL_CL4_DEFAULT 0x00282550 +#define mmA2S_CNTL_SW0_DEFAULT 0x08080005 +#define mmA2S_CNTL_SW1_DEFAULT 0x08080205 +#define mmA2S_CNTL_SW2_DEFAULT 0x08080200 +#define mmNGDC_MGCG_CTRL_DEFAULT 0x00000080 +#define mmA2S_MISC_CNTL_DEFAULT 0x00000003 +#define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f +#define mmNGDC_RESERVED_0_DEFAULT 0x00000000 +#define mmNGDC_RESERVED_1_DEFAULT 0x00000000 +#define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 +#define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 +#define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 +#define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 +#define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 +#define mmS2A_MISC_CNTL_DEFAULT 0x00000000 +#define mmA2S_CNTL2_SEC_CL0_DEFAULT 0x00000006 +#define mmA2S_CNTL2_SEC_CL1_DEFAULT 0x00000006 +#define mmA2S_CNTL2_SEC_CL2_DEFAULT 0x00000006 +#define mmA2S_CNTL2_SEC_CL3_DEFAULT 0x00000006 +#define mmA2S_CNTL2_SEC_CL4_DEFAULT 0x00000006 + + +// addressBlock: nbif_sion_SIONDEC +// base address: 0x1400000 +#define ixSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL4_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL4_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL4_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL4_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL4_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL4_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL4_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL4_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL4_Req_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL4_Req_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL4_Req_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL4_Req_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL4_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL4_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL4_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL4_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL5_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL5_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL5_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL5_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL5_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL5_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL5_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL5_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL5_Req_BurstTarget_REG0_DEFAULT 0x00000000 +#define ixSION_CL5_Req_BurstTarget_REG1_DEFAULT 0x00000000 +#define ixSION_CL5_Req_TimeSlot_REG0_DEFAULT 0x00000000 +#define ixSION_CL5_Req_TimeSlot_REG1_DEFAULT 0x00000000 +#define ixSION_CL5_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL5_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL5_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL5_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +#define ixSION_CNTL_REG0_DEFAULT 0x00000000 +#define ixSION_CNTL_REG1_DEFAULT 0x00000000 + + +// addressBlock: syshub_mmreg_direct_syshubdirect +// base address: 0x1400000 +#define ixSYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 +#define ixSYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 +#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 +#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 +#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixDMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 +#define ixSYSHUB_CG_CNTL_DEFAULT 0x00082000 +#define ixSYSHUB_TRANS_IDLE_DEFAULT 0x00000000 +#define ixSYSHUB_HP_TIMER_DEFAULT 0x00000100 +#define ixSYSHUB_SCRATCH_DEFAULT 0x00000040 +#define ixSYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 +#define ixSYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 +#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 +#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 +#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixDMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 +#define ixDMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 + + +// addressBlock: gdc_ras_gdc_ras_regblk +// base address: 0x1400000 +#define ixGDC_RAS_LEAF0_CTRL_DEFAULT 0x00000000 +#define ixGDC_RAS_LEAF1_CTRL_DEFAULT 0x00000000 +#define ixGDC_RAS_LEAF2_CTRL_DEFAULT 0x00000000 +#define ixGDC_RAS_LEAF3_CTRL_DEFAULT 0x00000000 +#define ixGDC_RAS_LEAF4_CTRL_DEFAULT 0x00000000 +#define ixGDC_RAS_LEAF5_CTRL_DEFAULT 0x00000000 + + +// addressBlock: gdc_rst_GDCRST_DEC +// base address: 0x1400000 +#define ixSHUB_PF_FLR_RST_DEFAULT 0x00000000 +#define ixSHUB_GFX_DRV_MODE1_RST_DEFAULT 0x00000000 +#define ixSHUB_LINK_RESET_DEFAULT 0x00000000 +#define ixSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000 +#define ixSHUB_HARD_RST_CTRL_DEFAULT 0x0000001b +#define ixSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009 +#define ixSHUB_SDP_PORT_RST_DEFAULT 0x00000000 + + +// addressBlock: bif_bx_pf_SYSDEC +// base address: 0x0 +#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000 +#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000 +#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000 +#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000 +#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000 +#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000 +#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000 +#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 +#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 + + +// addressBlock: bif_bx_pf_SYSPFVFDEC +// base address: 0x0 +#define mmMM_INDEX_DEFAULT 0x00000000 +#define mmMM_DATA_DEFAULT 0x00000000 +#define mmMM_INDEX_HI_DEFAULT 0x00000000 +#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 +#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 +#define mmPCIE_INDEX_DEFAULT 0x00000000 +#define mmPCIE_DATA_DEFAULT 0x00000000 +#define mmPCIE_INDEX2_DEFAULT 0x00000000 +#define mmPCIE_DATA2_DEFAULT 0x00000000 + + +// addressBlock: rcc_dwn_BIFDEC1 +// base address: 0x0 +#define mmDN_PCIE_RESERVED_DEFAULT 0x00000000 +#define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000 +#define mmDN_PCIE_CNTL_DEFAULT 0x00000000 +#define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 +#define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000 +#define mmDN_PCIE_STRAP_F0_DEFAULT 0x00000001 +#define mmDN_PCIE_STRAP_MISC_DEFAULT 0x00000000 +#define mmDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000 + + +// addressBlock: rcc_dwnp_BIFDEC1 +// base address: 0x0 +#define mmPCIEP_RESERVED_DEFAULT 0x00000000 +#define mmPCIEP_SCRATCH_DEFAULT 0x00000000 +#define mmPCIE_ERR_CNTL_DEFAULT 0x00000500 +#define mmPCIE_RX_CNTL_DEFAULT 0x00000000 +#define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 +#define mmPCIE_LC_CNTL2_DEFAULT 0x00000000 +#define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000 +#define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 + + +// addressBlock: rcc_ep_BIFDEC1 +// base address: 0x0 +#define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000 +#define mmEP_PCIE_CNTL_DEFAULT 0x00000100 +#define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000 +#define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000 +#define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000 +#define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080 +#define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000 +#define mmEP_PCIE_OBFF_CNTL_DEFAULT 0x00012774 +#define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00003468 +#define mmEP_PCIE_STRAP_MISC_DEFAULT 0x00000000 +#define mmEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000 +#define mmEP_PCIE_STRAP_PI_DEFAULT 0x00000000 +#define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 +#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 +#define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a +#define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000 +#define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000 +#define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000 +#define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +#define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500 +#define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000 +#define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 + + +// addressBlock: bif_bx_pf_BIFDEC1 +// base address: 0x0 +#define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 +#define mmBUS_CNTL_DEFAULT 0x00000000 +#define mmBIF_SCRATCH0_DEFAULT 0x00000000 +#define mmBIF_SCRATCH1_DEFAULT 0x00000000 +#define mmBX_RESET_EN_DEFAULT 0x00010003 +#define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000 +#define mmBX_RESET_CNTL_DEFAULT 0x00000000 +#define mmINTERRUPT_CNTL_DEFAULT 0x00000010 +#define mmINTERRUPT_CNTL2_DEFAULT 0x00000000 +#define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0 +#define mmCLKREQB_PERF_COUNTER_DEFAULT 0x00000000 +#define mmBIF_CLK_CTRL_DEFAULT 0x00000000 +#define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 +#define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000 +#define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 +#define mmBIF_SLVARB_MODE_DEFAULT 0x00000000 +#define mmBIF_FB_EN_DEFAULT 0x00000000 +#define mmBIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f +#define mmBIF_PERFMON_CNTL_DEFAULT 0x00000000 +#define mmBIF_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 +#define mmBIF_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 +#define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 +#define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 +#define mmBACO_CNTL_DEFAULT 0x00000000 +#define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 +#define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x00000100 +#define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 +#define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000400 +#define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000100 +#define mmMEM_TYPE_CNTL_DEFAULT 0x00000000 +#define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000 +#define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc +#define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000 +#define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc +#define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000 +#define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc +#define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000 +#define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc +#define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00 +#define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc +#define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00 +#define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc +#define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000 +#define mmBIF_VDDGFX_FB_CMP_DEFAULT 0x00000000 +#define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780 +#define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc +#define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800 +#define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c +#define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c +#define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 +#define mmBIF_RB_CNTL_DEFAULT 0x00000000 +#define mmBIF_RB_BASE_DEFAULT 0x00000000 +#define mmBIF_RB_RPTR_DEFAULT 0x00000000 +#define mmBIF_RB_WPTR_DEFAULT 0x00000000 +#define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmMAILBOX_INDEX_DEFAULT 0x00000000 +#define mmBIF_GPUIOV_RESET_NOTIFICATION_DEFAULT 0x00000000 +#define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +#define mmBIF_GMI_WRR_WEIGHT_DEFAULT 0x00202020 +#define mmNBIF_STRAP_WRITE_CTRL_DEFAULT 0x00000000 +#define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 +#define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 +#define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 +#define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 + + +// addressBlock: rcc_pf_0_BIFDEC1 +// base address: 0x0 +#define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000 +#define mmRCC_RESET_EN_DEFAULT 0x00008000 +#define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000 +#define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000 +#define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000 +#define mmRCC_BUS_CNTL_DEFAULT 0x00000000 +#define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000 +#define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000 +#define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000 +#define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000 +#define mmRCC_XDMA_LO_DEFAULT 0x00000000 +#define mmRCC_XDMA_HI_DEFAULT 0x00000000 +#define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 +#define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000 +#define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000 +#define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000 +#define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000 +#define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000 +#define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000 +#define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000 +#define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000 +#define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000 +#define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000 +#define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000 +#define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000 +#define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000 +#define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000 +#define mmRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000 +#define mmRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000 +#define mmRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000 +#define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00000000 +#define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000 +#define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000 +#define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000 + + +// addressBlock: rcc_pf_0_BIFDEC2 +// base address: 0x0 +#define mmGFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 +#define mmGFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 +#define mmGFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +#define mmGFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 +#define mmGFXMSIX_PBA_DEFAULT 0x00000000 + + +// addressBlock: rcc_strap_BIFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0 +#define mmRCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e +#define mmRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009 +#define mmRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 +#define mmRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 +#define mmRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 +#define mmRCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002 +#define mmRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000 +#define mmRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 +#define mmRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000 +#define mmRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001 +#define mmRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042 +#define mmRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022 +#define mmRCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002 +#define mmRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000 +#define mmRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001 +#define mmRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 +#define mmRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022 +#define mmRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 + + +// addressBlock: bif_bx_pf_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BME_STATUS_DEFAULT 0x00000000 +#define mmBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 +#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 +#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 +#define mmDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000000 +#define mmHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 +#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 +#define mmGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 +#define mmGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 +#define mmBIF_TRANS_PENDING_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 +#define mmMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 +#define mmMAILBOX_CONTROL_DEFAULT 0x00000000 +#define mmMAILBOX_INT_CNTL_DEFAULT 0x00000000 +#define mmBIF_VMHV_MAILBOX_DEFAULT 0x00000000 + + +// addressBlock: rcc_pf_0_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DOORBELL_APER_EN_DEFAULT 0x00000000 +#define mmRCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 +#define mmRCC_CONFIG_RESERVED_DEFAULT 0x00000000 +#define mmRCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 + + +// addressBlock: syshub_mmreg_ind_syshubdec +// base address: 0x0 +#define mmSYSHUB_INDEX_DEFAULT 0x00000000 +#define mmSYSHUB_DATA_DEFAULT 0x00000000 + + +// addressBlock: rcc_strap_rcc_strap_internal +// base address: 0x10100000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 +#define mmRCC_DEV1_PORT_STRAP0_DEFAULT 0x00000000 +#define mmRCC_DEV1_PORT_STRAP1_DEFAULT 0x00000000 +#define mmRCC_DEV1_PORT_STRAP2_DEFAULT 0x00000000 +#define mmRCC_DEV1_PORT_STRAP3_DEFAULT 0x00000000 +#define mmRCC_DEV1_PORT_STRAP4_DEFAULT 0x00000000 +#define mmRCC_DEV1_PORT_STRAP5_DEFAULT 0x00000000 +#define mmRCC_DEV1_PORT_STRAP6_DEFAULT 0x00000000 +#define mmRCC_DEV1_PORT_STRAP7_DEFAULT 0x00000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF2_STRAP0_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF2_STRAP2_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF2_STRAP3_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF2_STRAP4_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF2_STRAP5_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF2_STRAP6_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF2_STRAP13_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF3_STRAP0_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF3_STRAP2_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF3_STRAP3_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF3_STRAP4_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF3_STRAP5_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF3_STRAP6_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF3_STRAP13_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF4_STRAP0_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF4_STRAP2_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF4_STRAP3_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF4_STRAP4_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF4_STRAP5_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF4_STRAP6_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF4_STRAP13_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF5_STRAP0_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF5_STRAP2_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF5_STRAP3_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF5_STRAP4_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF5_STRAP5_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF5_STRAP6_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF5_STRAP13_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF6_STRAP0_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF6_STRAP2_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF6_STRAP3_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF6_STRAP4_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF6_STRAP5_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF6_STRAP6_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF6_STRAP13_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF7_STRAP0_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF7_STRAP2_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF7_STRAP3_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF7_STRAP4_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF7_STRAP5_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF7_STRAP6_DEFAULT 0x00000000 +#define mmRCC_DEV0_EPF7_STRAP13_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF0_STRAP0_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF0_STRAP2_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF0_STRAP3_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF0_STRAP4_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF0_STRAP5_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF0_STRAP6_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF0_STRAP13_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF1_STRAP0_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF1_STRAP2_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF1_STRAP3_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF1_STRAP4_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF1_STRAP5_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF1_STRAP6_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF1_STRAP13_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF2_STRAP0_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF2_STRAP2_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF2_STRAP3_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF2_STRAP4_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF2_STRAP5_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF2_STRAP6_DEFAULT 0x00000000 +#define mmRCC_DEV1_EPF2_STRAP13_DEFAULT 0x00000000 + + +// addressBlock: bif_rst_bif_rst_regblk +// base address: 0x10100000 +#define ixHARD_RST_CTRL_DEFAULT 0xb0000055 +#define ixRSMU_SOFT_RST_CTRL_DEFAULT 0x90000000 +#define ixSELF_SOFT_RST_DEFAULT 0x00000000 +#define ixGFX_DRV_MODE1_RST_CTRL_DEFAULT 0x000000a9 +#define ixBIF_RST_MISC_CTRL_DEFAULT 0x00000644 +#define ixBIF_RST_MISC_CTRL2_DEFAULT 0x00000000 +#define ixBIF_RST_MISC_CTRL3_DEFAULT 0x00004900 +#define ixBIF_RST_GFXVF_FLR_IDLE_DEFAULT 0x00000000 +#define ixDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x0206a9a9 +#define ixDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009 +#define ixDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009 +#define ixDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009 +#define ixDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009 +#define ixDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009 +#define ixDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009 +#define ixDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009 +#define ixBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000 +#define ixBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000 +#define ixBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000 +#define ixBIF_POWER_INTR_STS_DEFAULT 0x00000000 +#define ixBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000 +#define ixBIF_PF0_VF_FLR_INTR_STS_DEFAULT 0x00000000 +#define ixBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000 +#define ixBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000 +#define ixBIF_D3HOTD0_INTR_MASK_DEFAULT 0x000000ff +#define ixBIF_POWER_INTR_MASK_DEFAULT 0x00000000 +#define ixBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000 +#define ixBIF_PF0_VF_FLR_INTR_MASK_DEFAULT 0x00000000 +#define ixBIF_PF_FLR_RST_DEFAULT 0x00000000 +#define ixBIF_PF0_VF_FLR_RST_DEFAULT 0x00000000 +#define ixBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000 +#define ixBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000 +#define ixBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000 +#define ixBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000 +#define ixBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000 +#define ixBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000 +#define ixBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000 +#define ixBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000 +#define ixDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define ixDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define ixDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define ixDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define ixDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define ixDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define ixDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define ixDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +#define ixBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000 + + +// addressBlock: bif_misc_bif_misc_regblk +// base address: 0x10100000 +#define ixMISC_SCRATCH_DEFAULT 0x00000000 +#define ixINTR_LINE_POLARITY_DEFAULT 0x00000000 +#define ixINTR_LINE_ENABLE_DEFAULT 0x00000000 +#define ixOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf +#define ixBIFC_MISC_CTRL0_DEFAULT 0x08000004 +#define ixBIFC_MISC_CTRL1_DEFAULT 0x00008004 +#define ixBIFC_BME_ERR_LOG_DEFAULT 0x00000000 +#define ixBIFC_RCCBIH_BME_ERR_LOG_DEFAULT 0x00000000 +#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x00000000 +#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x00000000 +#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x00000000 +#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x00000000 +#define ixNBIF_VWIRE_CTRL_DEFAULT 0x00000000 +#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 +#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 +#define ixNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000 +#define ixNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000 +#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000 +#define ixNBIF_MGCG_CTRL_DEFAULT 0x00000080 +#define ixNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000 +#define ixSMN_MST_CNTL0_DEFAULT 0x00000001 +#define ixSMN_MST_EP_CNTL1_DEFAULT 0x00000000 +#define ixSMN_MST_EP_CNTL2_DEFAULT 0x00000000 +#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 +#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 +#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000 +#define ixNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000 +#define ixBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa +#define ixBIFC_THT_CNTL_DEFAULT 0x00000222 +#define ixBIFC_HSTARB_CNTL_DEFAULT 0x00000000 +#define ixBIFC_GSI_CNTL_DEFAULT 0x000017c0 +#define ixBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000 +#define ixBIFC_SDP_CNTL_0_DEFAULT 0x003cf3cf +#define ixBIFC_PERF_CNTL_0_DEFAULT 0x00000000 +#define ixBIFC_PERF_CNTL_1_DEFAULT 0x00000000 +#define ixBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000 +#define ixBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000 +#define ixBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000 +#define ixBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000 +#define ixNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000 +#define ixSMN_MST_EP_CNTL3_DEFAULT 0x00000000 +#define ixSMN_MST_EP_CNTL4_DEFAULT 0x00000000 +#define ixBIF_SELFRING_BUFFER_VID_DEFAULT 0x0000605f +#define ixBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: bif_ras_bif_ras_regblk +// base address: 0x10100000 +#define ixBIF_RAS_LEAF0_CTRL_DEFAULT 0x00000000 +#define ixBIF_RAS_LEAF1_CTRL_DEFAULT 0x00000000 +#define ixBIF_RAS_LEAF2_CTRL_DEFAULT 0x00000000 +#define ixBIF_RAS_MISC_CTRL_DEFAULT 0x00000000 +#define ixBIF_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000 +#define ixBIF_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000 + + +// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC +// base address: 0x10134000 +#define ixRCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define ixRCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define ixRCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define ixRCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define ixRCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define ixRCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define ixRCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define ixRCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define ixRCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC +// base address: 0x10134200 +#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 + + +// addressBlock: pciemsix_amdgfx_MSIXTDEC +// base address: 0x10170000 +#define ixPCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 +#define ixPCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: pciemsix_amdgfx_MSIXPDEC +// base address: 0x10171000 +#define ixPCIEMSIX_PBA_DEFAULT 0x00000000 + + +// addressBlock: syshub_mmreg_ind_syshubind +// base address: 0x0 +#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 +#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 +#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 +#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL_DEFAULT 0x00082000 +#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000 +#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER_DEFAULT 0x00000100 +#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH_DEFAULT 0x00000040 +#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 +#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 +#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 +#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 + +#endif |