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authorLinus Torvalds <torvalds@linux-foundation.org>2017-05-03 11:44:24 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2017-05-03 11:44:24 -0700
commit2f34c1231bfc9f2550f934acb268ac7315fb3837 (patch)
treeff8114b3b4ec4723a11b041c6b74c389e9f0eeb9 /drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
parenta3719f34fdb664ffcfaec2160ef20fca7becf2ee (diff)
parent8b03d1ed2c43a2ba5ef3381322ee4515b97381bf (diff)
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Merge tag 'drm-for-v4.12' of git://people.freedesktop.org/~airlied/linux
Pull drm u pdates from Dave Airlie: "This is the main drm pull request for v4.12. Apart from two fixes pulls, everything should have been in drm-next for at least 2 weeks. The biggest thing in here is AMD released the public headers for their upcoming VEGA GPUs. These as always are quite a sizeable chunk of header files. They've also added initial non-display support for those GPUs, though they aren't available in production yet. Otherwise it's pretty much normal. New bridge drivers: - megachips-stdpxxxx-ge-b850v3-fw LVDS->DP++ - generic LVDS bridge support. Core: - Displayport link train failure reporting to userspace - debugfs interface cleaned up - subsystem TODO in kerneldoc now - Extended fbdev support (flipping and vblank wait) - drm_platform removed - EDP CRC support in helper - HF-VSDB SCDC support in EDID parser - Lots of code cleanups and header extraction - Thunderbolt external GPU awareness - Atomic helper improvements - Documentation improvements panel: - Sitronix and Samsung new panel support amdgpu: - Preliminary vega10 support - Multi-level page table support - GPU sensor support for userspace - PRT support for sparse buffers - SR-IOV improvements - Non-contig VRAM CPU mapping i915: - Atomic modesetting enabled by default on Gen5+ - LSPCON improvements - Atomic state handling for cdclk - GPU reset improvements - In-kernel unit tests - Geminilake improvements and color manager support - Designware i2c fixes - vblank evasion improvements - Hotplug safe connector iterators - GVT scheduler QoS support - GVT Kabylake support nouveau: - Acceleration support for Pascal (GP10x). - Rearchitecture of code handling proprietary signed firmware - Fix GTX 970 with odd MMU configuration - GP10B support - GP107 acceleration support vmwgfx: - Atomic modesetting support for vmwgfx omapdrm: - Support for render nodes - Refactor omapdss code - Fix some probe ordering issues - Fix too dark RGB565 rendering sunxi: - prelim rework for multiple pipes. mali-dp: - Color management support - Plane scaling - Power management improvements imx-drm: - Prefetch Resolve Engine/Gasket on i.MX6QP - Deferred plane disabling - Separate alpha support mediatek: - Mediatek SoC MT2701 support rcar-du: - Gen3 HDMI support msm: - 4k support for newer chips - OPP bindings for gpu - prep work for per-process pagetables vc4: - HDMI audio support - fixes qxl: - minor fixes. dw-hdmi: - PHY improvements - CSC fixes - Amlogic GX SoC support" * tag 'drm-for-v4.12' of git://people.freedesktop.org/~airlied/linux: (1778 commits) drm/nouveau/fb/gf100-: Fix 32 bit wraparound in new ram detection drm/nouveau/secboot/gm20b: fix the error return code in gm20b_secboot_tegra_read_wpr() drm/nouveau/kms: Increase max retries in scanout position queries. drm/nouveau/bios/bitP: check that table is long enough for optional pointers drm/nouveau/fifo/nv40: no ctxsw for pre-nv44 mpeg engine drm: mali-dp: use div_u64 for expensive 64-bit divisions drm/i915: Confirm the request is still active before adding it to the await drm/i915: Avoid busy-spinning on VLV_GLTC_PW_STATUS mmio drm/i915/selftests: Allocate inode/file dynamically drm/i915: Fix system hang with EI UP masked on Haswell drm/i915: checking for NULL instead of IS_ERR() in mock selftests drm/i915: Perform link quality check unconditionally during long pulse drm/i915: Fix use after free in lpe_audio_platdev_destroy() drm/i915: Use the right mapping_gfp_mask for final shmem allocation drm/i915: Make legacy cursor updates more unsynced drm/i915: Apply a cond_resched() to the saturated signaler drm/i915: Park the signaler before sleeping drm: mali-dp: Check the mclk rate and allow up/down scaling drm: mali-dp: Enable image enhancement when scaling drm: mali-dp: Add plane upscaling support ...
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h194
1 files changed, 194 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
new file mode 100644
index 000000000000..0cbae8bafbf2
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _thm_9_0_DEFAULT_HEADER
+#define _thm_9_0_DEFAULT_HEADER
+
+
+// addressBlock: thm_thm_SmuThmDec
+#define mmTHM_TCON_CUR_TMP_DEFAULT 0x00000000
+#define mmTHM_TCON_HTC_DEFAULT 0x00004000
+#define mmTHM_TCON_THERM_TRIP_DEFAULT 0x00000001
+#define mmTHM_GPIO_PROCHOT_CTRL_DEFAULT 0x000000f9
+#define mmTHM_GPIO_THERMTRIP_CTRL_DEFAULT 0x001000f9
+#define mmTHM_GPIO_PWM_CTRL_DEFAULT 0x000000f9
+#define mmTHM_GPIO_TACHIN_CTRL_DEFAULT 0x000000f9
+#define mmTHM_GPIO_PUMPOUT_CTRL_DEFAULT 0x000000f9
+#define mmTHM_GPIO_PUMPIN_CTRL_DEFAULT 0x000000f9
+#define mmTHM_THERMAL_INT_ENA_DEFAULT 0x00000000
+#define mmTHM_THERMAL_INT_CTRL_DEFAULT 0x0fff0078
+#define mmTHM_THERMAL_INT_STATUS_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL0_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL1_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL2_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL3_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL4_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL5_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL6_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL7_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL8_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL9_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL10_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL11_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL12_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL13_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL14_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIL15_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR0_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR1_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR2_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR3_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR4_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR5_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR6_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR7_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR8_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR9_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR10_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR11_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR12_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR13_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR14_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_RDIR15_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_INT_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON0_DEBUG_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL0_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL1_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL2_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL3_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL4_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL5_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL6_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL7_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL8_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL9_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL10_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL11_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL12_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL13_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL14_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIL15_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR0_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR1_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR2_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR3_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR4_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR5_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR6_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR7_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR8_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR9_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR10_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR11_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR12_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR13_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR14_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_RDIR15_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_INT_DATA_DEFAULT 0x00000000
+#define mmTHM_TMON1_DEBUG_DEFAULT 0x00000000
+#define mmTHM_DIE1_TEMP_DEFAULT 0x00000000
+#define mmTHM_DIE2_TEMP_DEFAULT 0x00000000
+#define mmTHM_DIE3_TEMP_DEFAULT 0x00000000
+#define mmCG_MULT_THERMAL_CTRL_DEFAULT 0x08400001
+#define mmCG_MULT_THERMAL_STATUS_DEFAULT 0x00000000
+#define mmTHM_TMON0_COEFF_DEFAULT 0x00024068
+#define mmTHM_TMON1_COEFF_DEFAULT 0x00024068
+#define mmCG_FDO_CTRL0_DEFAULT 0x0000642c
+#define mmCG_FDO_CTRL1_DEFAULT 0x001e1f7d
+#define mmCG_FDO_CTRL2_DEFAULT 0x02bf0228
+#define mmCG_TACH_CTRL_DEFAULT 0x00008002
+#define mmCG_TACH_STATUS_DEFAULT 0x00000000
+#define mmCG_THERMAL_STATUS_DEFAULT 0x00000000
+#define mmCG_PUMP_CTRL0_DEFAULT 0x0000642c
+#define mmCG_PUMP_CTRL1_DEFAULT 0x001e1f7d
+#define mmCG_PUMP_CTRL2_DEFAULT 0x02bf0228
+#define mmCG_PUMP_TACH_CTRL_DEFAULT 0x00008002
+#define mmCG_PUMP_TACH_STATUS_DEFAULT 0x00000000
+#define mmCG_PUMP_STATUS_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL0_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL1_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL2_DEFAULT 0x00000060
+#define mmTHM_TCON_LOCAL3_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL4_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL5_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL6_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL7_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL8_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL9_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL10_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL11_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL12_DEFAULT 0x00000000
+#define mmTHM_TCON_LOCAL13_DEFAULT 0x00000000
+#define mmTHM_BACO_CNTL_DEFAULT 0x00000004
+#define mmTHM_BACO_TIMING0_DEFAULT 0x80a06050
+#define mmTHM_BACO_TIMING1_DEFAULT 0x1020f070
+#define mmXTAL_CNTL_DEFAULT 0x00006010
+#define mmSBTSI_REMOTE_TEMP_DEFAULT 0x00000000
+#define mmSBRMI_CONTROL_DEFAULT 0x00000000
+#define mmSBRMI_COMMAND_DEFAULT 0x00000000
+#define mmSBRMI_WRITE_DATA0_DEFAULT 0x00000000
+#define mmSBRMI_WRITE_DATA1_DEFAULT 0x00000000
+#define mmSBRMI_WRITE_DATA2_DEFAULT 0x00000000
+#define mmSBRMI_READ_DATA0_DEFAULT 0x00000000
+#define mmSBRMI_READ_DATA1_DEFAULT 0x00000000
+#define mmSBRMI_CORE_EN_NUMBER_DEFAULT 0x00000010
+#define mmSBRMI_CORE_EN_STATUS0_DEFAULT 0x00000000
+#define mmSBRMI_CORE_EN_STATUS1_DEFAULT 0x00000000
+#define mmSBRMI_APIC_STATUS0_DEFAULT 0x00000000
+#define mmSBRMI_APIC_STATUS1_DEFAULT 0x00000000
+#define mmSBRMI_MCE_STATUS0_DEFAULT 0x00000000
+#define mmSBRMI_MCE_STATUS1_DEFAULT 0x00000000
+#define mmSMBUS_CNTL0_DEFAULT 0x00030082
+#define mmSMBUS_CNTL1_DEFAULT 0x0000063f
+#define mmSMBUS_BLKWR_CMD_CTRL0_DEFAULT 0x12110201
+#define mmSMBUS_BLKWR_CMD_CTRL1_DEFAULT 0x0003005a
+#define mmSMBUS_BLKRD_CMD_CTRL0_DEFAULT 0x00001303
+#define mmSMBUS_BLKRD_CMD_CTRL1_DEFAULT 0x00000000
+#define mmSMBUS_TIMING_CNTL0_DEFAULT 0x028a4f5c
+#define mmSMBUS_TIMING_CNTL1_DEFAULT 0x08036927
+#define mmSMBUS_TIMING_CNTL2_DEFAULT 0x0021e548
+#define mmSMBUS_TRIGGER_CNTL_DEFAULT 0x00000000
+#define mmSMBUS_UDID_CNTL0_DEFAULT 0x7fffffff
+#define mmSMBUS_UDID_CNTL1_DEFAULT 0x00000000
+#define mmSMBUS_UDID_CNTL2_DEFAULT 0x00000043
+#define mmSMBUS_BACO_DUMMY_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE0_LOW_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE0_HIGH_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE1_LOW_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE1_HIGH_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE2_LOW_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE2_HIGH_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE3_LOW_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE3_HIGH_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE4_LOW_DEFAULT 0x00000000
+#define mmSMBUS_BACO_ADDR_RANGE4_HIGH_DEFAULT 0x00000000
+#define mmTHM_GPIO_MACO_EN_CTRL_DEFAULT 0x000000f9
+#define mmTHM_BACO_TIMING2_DEFAULT 0x00903040
+#define mmTHM_BACO_TIMING_DEFAULT 0x00000a8c
+#define mmTHM_TMON0_REMOTE_START_DEFAULT 0x00000000
+#define mmTHM_TMON0_REMOTE_END_DEFAULT 0x00000000
+#define mmTHM_TMON1_REMOTE_START_DEFAULT 0x00000000
+#define mmTHM_TMON1_REMOTE_END_DEFAULT 0x00000000
+#define mmTHM_TMON2_REMOTE_START_DEFAULT 0x00000000
+#define mmTHM_TMON2_REMOTE_END_DEFAULT 0x00000000
+#define mmTHM_TMON3_REMOTE_START_DEFAULT 0x00000000
+#define mmTHM_TMON3_REMOTE_END_DEFAULT 0x00000000
+
+#endif