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author | Rex Zhu <Rex.Zhu@amd.com> | 2018-06-20 15:05:04 +0800 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-07-05 16:40:02 -0500 |
commit | 20582319bce482e65ee1f417b9867f028d058c12 (patch) | |
tree | 91ebd6be19f46cbc3c329d072941c88aa75f0e4c /drivers/gpu/drm/amd/include/dm_pp_interface.h | |
parent | 70b63170c3effc1d9a66fbfe4a5702c8cbbd31c3 (diff) | |
download | linux-20582319bce482e65ee1f417b9867f028d058c12.tar.gz linux-20582319bce482e65ee1f417b9867f028d058c12.tar.bz2 linux-20582319bce482e65ee1f417b9867f028d058c12.zip |
drm/amd/pp: Remove the same struct define in powerplay
delete the same struct define in powerplay, share the struct
with display.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/dm_pp_interface.h')
-rw-r--r-- | drivers/gpu/drm/amd/include/dm_pp_interface.h | 37 |
1 files changed, 2 insertions, 35 deletions
diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h index 7852952d1fde..1d93a0c574c9 100644 --- a/drivers/gpu/drm/amd/include/dm_pp_interface.h +++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h @@ -23,6 +23,8 @@ #ifndef _DM_PP_INTERFACE_ #define _DM_PP_INTERFACE_ +#include "dm_services_types.h" + #define PP_MAX_CLOCK_LEVELS 16 enum amd_pp_display_config_type{ @@ -189,39 +191,4 @@ struct pp_display_clock_request { uint32_t clock_freq_in_khz; }; -#define PP_MAX_WM_SETS 4 - -enum pp_wm_set_id { - DC_WM_SET_A = 0, - DC_WM_SET_B, - DC_WM_SET_C, - DC_WM_SET_D, - DC_WM_SET_INVALID = 0xffff, -}; - -struct pp_wm_set_with_dmif_clock_range_soc15 { - enum pp_wm_set_id wm_set_id; - uint32_t wm_min_dcefclk_in_khz; - uint32_t wm_max_dcefclk_in_khz; - uint32_t wm_min_memclk_in_khz; - uint32_t wm_max_memclk_in_khz; -}; - -struct pp_wm_set_with_mcif_clock_range_soc15 { - enum pp_wm_set_id wm_set_id; - uint32_t wm_min_socclk_in_khz; - uint32_t wm_max_socclk_in_khz; - uint32_t wm_min_memclk_in_khz; - uint32_t wm_max_memclk_in_khz; -}; - -struct pp_wm_sets_with_clock_ranges_soc15 { - uint32_t num_wm_sets_dmif; - uint32_t num_wm_sets_mcif; - struct pp_wm_set_with_dmif_clock_range_soc15 - wm_sets_dmif[PP_MAX_WM_SETS]; - struct pp_wm_set_with_mcif_clock_range_soc15 - wm_sets_mcif[PP_MAX_WM_SETS]; -}; - #endif /* _DM_PP_INTERFACE_ */ |