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| author | Evan Quan <evan.quan@amd.com> | 2019-10-10 11:40:37 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-10-15 15:48:29 -0400 |
| commit | 7e899409fd5e9abccee8435d9401b8ca12cebcae (patch) | |
| tree | 8f8ef00c66a17ade8be31850b6cc978b49fc21a0 /drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | |
| parent | 06615f9a0c0d68566fc069729aade64a7dbadd58 (diff) | |
| download | linux-7e899409fd5e9abccee8435d9401b8ca12cebcae.tar.gz linux-7e899409fd5e9abccee8435d9401b8ca12cebcae.tar.bz2 linux-7e899409fd5e9abccee8435d9401b8ca12cebcae.zip | |
drm/amd/powerplay: enable df cstate control on swSMU routine
Currently this is only supported on Vega20 with 40.50 and later
SMC firmware.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/amdgpu_smu.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index c9266ea70331..8bb5287fe711 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -1834,6 +1834,29 @@ int smu_set_mp1_state(struct smu_context *smu, return ret; } +int smu_set_df_cstate(struct smu_context *smu, + enum pp_df_cstate state) +{ + int ret = 0; + + /* + * The SMC is not fully ready. That may be + * expected as the IP may be masked. + * So, just return without error. + */ + if (!smu->pm_enabled) + return 0; + + if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) + return 0; + + ret = smu->ppt_funcs->set_df_cstate(smu, state); + if (ret) + pr_err("[SetDfCstate] failed!\n"); + + return ret; +} + const struct amd_ip_funcs smu_ip_funcs = { .name = "smu", .early_init = smu_early_init, |