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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2020-03-06 10:08:10 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2020-03-06 10:08:10 +0800 |
| commit | a61ac1e75105a077ec1efd6923ae3c619f862304 (patch) | |
| tree | 31a24e8ae27e3d124e237802c403746dc5108ee2 /drivers/gpu/drm/i915/gvt/gvt.h | |
| parent | 8fde41076f6df53db84cb13051efed6482986ce3 (diff) | |
| download | linux-a61ac1e75105a077ec1efd6923ae3c619f862304.tar.gz linux-a61ac1e75105a077ec1efd6923ae3c619f862304.tar.bz2 linux-a61ac1e75105a077ec1efd6923ae3c619f862304.zip | |
drm/i915/gvt: Wean gvt off using dev_priv
Teach gvt to use intel_gt directly as it currently assumes direct HW
access.
[Zhenyu: rebase, fix compiling]
Cc: Ding Zhuocheng <zhuocheng.ding@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200304032307.2983-3-zhenyuw@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/gvt.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/gvt.h | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 8cf292a8d6bd..58c2c7932e3f 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -286,7 +286,7 @@ struct intel_gvt { /* scheduler scope lock, protect gvt and vgpu schedule related data */ struct mutex sched_lock; - struct drm_i915_private *dev_priv; + struct intel_gt *gt; struct idr vgpu_idr; /* vGPU IDR pool */ struct intel_gvt_device_info device_info; @@ -356,14 +356,15 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt); #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) #define HOST_FENCE 4 +#define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt) + /* Aperture/GM space definitions for GVT device */ -#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) -#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start) +#define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end +#define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start -#define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.vm.total) -#define gvt_ggtt_sz(gvt) \ - ((gvt->dev_priv->ggtt.vm.total >> PAGE_SHIFT) << 3) -#define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) +#define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total +#define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3) +#define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) #define gvt_aperture_gmadr_base(gvt) (0) #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ @@ -374,7 +375,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt); #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ + gvt_hidden_sz(gvt) - 1) -#define gvt_fence_sz(gvt) ((gvt)->dev_priv->ggtt.num_fences) +#define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences) /* Aperture/GM space definitions for vGPU */ #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) @@ -565,14 +566,14 @@ enum { GVT_FAILSAFE_GUEST_ERR, }; -static inline void mmio_hw_access_pre(struct drm_i915_private *dev_priv) +static inline void mmio_hw_access_pre(struct intel_gt *gt) { - intel_runtime_pm_get(&dev_priv->runtime_pm); + intel_runtime_pm_get(gt->uncore->rpm); } -static inline void mmio_hw_access_post(struct drm_i915_private *dev_priv) +static inline void mmio_hw_access_post(struct intel_gt *gt) { - intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); + intel_runtime_pm_put_unchecked(gt->uncore->rpm); } /** |