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| author | Ping Gao <ping.a.gao@intel.com> | 2016-10-27 14:46:40 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2016-11-07 14:16:58 +0800 |
| commit | 5f399f1158959a112d98ade5380464da29ba646c (patch) | |
| tree | 59eb0a6700928d18e4282632550477c57c1d1071 /drivers/gpu/drm/i915/gvt/handlers.c | |
| parent | 337d0665270ad1ebcbd58ddc1ce7769852f2391b (diff) | |
| download | linux-5f399f1158959a112d98ade5380464da29ba646c.tar.gz linux-5f399f1158959a112d98ade5380464da29ba646c.tar.bz2 linux-5f399f1158959a112d98ade5380464da29ba646c.zip | |
drm/i915/gvt: add write vreg in MMIO DMA_CTRL handler
Missing write_vreg in DMA_CTRL write handler would make obsolete
value return when read vreg.
v2: get data from vreg after updating it.
Signed-off-by: Ping Gao <ping.a.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/handlers.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/handlers.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 9ab1f95dddc5..0b62f4621a85 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1158,7 +1158,10 @@ static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { - u32 mode = *(u32 *)p_data; + u32 mode; + + write_vreg(vgpu, offset, p_data, bytes); + mode = vgpu_vreg(vgpu, offset); if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", |