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| author | Jani Nikula <jani.nikula@intel.com> | 2020-06-29 11:09:53 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2020-06-29 11:09:54 +0300 |
| commit | cd65bbb4d8c90079f2f4d114bd0a967718d53476 (patch) | |
| tree | f89af81601f996ee3aa7841e8f5241e64547777e /drivers/gpu/drm/i915/gvt/reg.h | |
| parent | 9ebcfadb0610322ac537dd7aa5d9cbc2b2894c68 (diff) | |
| parent | a291e4fba259a56a6a274c1989997acb6f0bb03a (diff) | |
| download | linux-cd65bbb4d8c90079f2f4d114bd0a967718d53476.tar.gz linux-cd65bbb4d8c90079f2f4d114bd0a967718d53476.tar.bz2 linux-cd65bbb4d8c90079f2f4d114bd0a967718d53476.zip | |
Merge tag 'gvt-fixes-2020-06-17' of https://github.com/intel/gvt-linux into drm-intel-fixes
gvt-fixes-2020-06-17
- Two missed MMIO handler fixes for SKL/CFL (Colin)
- Fix mask register bits check (Colin)
- Fix one lockdep error for debugfs entry access (Colin)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200617043418.GQ5687@zhen-hp.sh.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/reg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h index 5b66e14c5b7b..b88e033cbed4 100644 --- a/drivers/gpu/drm/i915/gvt/reg.h +++ b/drivers/gpu/drm/i915/gvt/reg.h @@ -94,6 +94,11 @@ #define GFX_MODE_BIT_SET_IN_MASK(val, bit) \ ((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16)))) +#define IS_MASKED_BITS_ENABLED(_val, _b) \ + (((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b)) +#define IS_MASKED_BITS_DISABLED(_val, _b) \ + ((_val) & _MASKED_BIT_DISABLE(_b)) + #define FORCEWAKE_RENDER_GEN9_REG 0xa278 #define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84 #define FORCEWAKE_BLITTER_GEN9_REG 0xa188 |