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| author | Matt Roper <matthew.d.roper@intel.com> | 2022-06-01 08:07:25 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-06-02 07:21:09 -0700 |
| commit | 5ac342ef84d7dccd1ba43f5fa2dc10a6feda91e2 (patch) | |
| tree | 2646fb6d3c518a2bbda388e9b5e3d61a0b2c9a45 /drivers/gpu/drm/i915/i915_drv.h | |
| parent | b87d39019651c9cae169396cf5ae525393084490 (diff) | |
| download | linux-5ac342ef84d7dccd1ba43f5fa2dc10a6feda91e2.tar.gz linux-5ac342ef84d7dccd1ba43f5fa2dc10a6feda91e2.tar.bz2 linux-5ac342ef84d7dccd1ba43f5fa2dc10a6feda91e2.zip | |
drm/i915/pvc: Add SSEU changes
PVC splits the mask of enabled DSS over two registers. It also changes
the meaning of the EU fuse register such that each bit represents a
single EU rather than a pair of EUs.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-7-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ec1b3484fdaf..fbea4d1ede7c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1422,6 +1422,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) +#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) + /* i915_gem.c */ void i915_gem_init_early(struct drm_i915_private *dev_priv); void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); |