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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-11-07 11:05:40 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-11-08 18:10:10 +0100 |
| commit | c42664cceb368ee04848e23a9964afd953a9145c (patch) | |
| tree | b4f29ca4cbb58fb558b547cd794ce422df99a438 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 40c499f93fdefa2c496f59d18483b417ea06448b (diff) | |
| download | linux-c42664cceb368ee04848e23a9964afd953a9145c.tar.gz linux-c42664cceb368ee04848e23a9964afd953a9145c.tar.bz2 linux-c42664cceb368ee04848e23a9964afd953a9145c.zip | |
drm/i915: Optimize pipe irq handling on bdw
We have a per-pipe bit in the master irq control register, so use it.
This allows us to drop the masks for aggregate interrupt bits and be a
bit more explicit in the code. It also removes one indentation level.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2b9e66c0c6cf..f150edaa64ca 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4031,15 +4031,12 @@ #define GEN8_DE_PIPE_C_IRQ (1<<18) #define GEN8_DE_PIPE_B_IRQ (1<<17) #define GEN8_DE_PIPE_A_IRQ (1<<16) +#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) #define GEN8_GT_VECS_IRQ (1<<6) #define GEN8_GT_VCS2_IRQ (1<<3) #define GEN8_GT_VCS1_IRQ (1<<2) #define GEN8_GT_BCS_IRQ (1<<1) #define GEN8_GT_RCS_IRQ (1<<0) -/* Lazy definition */ -#define GEN8_GT_IRQS 0x000000ff -#define GEN8_DE_IRQS 0x01ff0000 -#define GEN8_RSVD_IRQS 0xB700ff00 #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) |