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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2009-08-17 13:31:43 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-09-04 13:05:38 -0700 |
| commit | 652c393a3368af84359da37c45afc35a91144960 (patch) | |
| tree | 35f76866301f0ee61819d6265068ca548d119c0e /drivers/gpu/drm/i915/i915_suspend.c | |
| parent | 043029655816ed4cfc2ed247020ef97e5d637392 (diff) | |
| download | linux-652c393a3368af84359da37c45afc35a91144960.tar.gz linux-652c393a3368af84359da37c45afc35a91144960.tar.bz2 linux-652c393a3368af84359da37c45afc35a91144960.zip | |
drm/i915: add dynamic clock frequency control
There are several sources of unnecessary power consumption on Intel
graphics systems. The first is the LVDS clock. TFTs don't suffer from
persistence issues like CRTs, and so we can reduce the LVDS refresh rate
when the screen is idle. It will be automatically upclocked when
userspace triggers graphical activity. Beyond that, we can enable memory
self refresh. This allows the memory to go into a lower power state when
the graphics are idle. Finally, we can drop some clocks on the gpu
itself. All of these things can be reenabled between frames when GPU
activity is triggered, and so there should be no user visible graphical
changes.
Signed-off-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_suspend.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_suspend.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 1d04e1904ac6..20d4d19f5568 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -461,7 +461,7 @@ int i915_save_state(struct drm_device *dev) /* Clock gating state */ dev_priv->saveD_STATE = I915_READ(D_STATE); - dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS); + dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Cache mode state */ dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); @@ -588,7 +588,7 @@ int i915_restore_state(struct drm_device *dev) /* Clock gating state */ I915_WRITE (D_STATE, dev_priv->saveD_STATE); - I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS); + I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); /* Cache mode state */ I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); |