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author | Imre Deak <imre.deak@intel.com> | 2016-04-04 15:42:57 +0300 |
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committer | Imre Deak <imre.deak@intel.com> | 2016-04-15 14:47:51 +0300 |
commit | 443a93ac89aa112b133dca6a23ca2d315253f6ae (patch) | |
tree | 3a88614541acc1fb56651859727d9fc5521d822b /drivers/gpu/drm/i915/intel_display.c | |
parent | a7c8125f464ce798fe0962e0fd837802e7bf28cc (diff) | |
download | linux-443a93ac89aa112b133dca6a23ca2d315253f6ae.tar.gz linux-443a93ac89aa112b133dca6a23ca2d315253f6ae.tar.bz2 linux-443a93ac89aa112b133dca6a23ca2d315253f6ae.zip |
drm/i915/skl: Unexport skl_pw1_misc_io_init
On Broxton we need to enable/disable power well 1 during the init/unit
display sequence similarly to Skylake/Kabylake. The code for this will
be added in a follow-up patch, but to prepare for that unexport
skl_pw1_misc_io_init(). It's a simple function called only from a single
place and having it inlined in the Skylake display core init/unit
functions will make it easier to compare it with its Broxton
counterpart.
This also flips the order of Misc IO and power well 1 disabling which
matches the enabling order. The specification doesn't prescribe the
disabling order, so this should be fine.
v2:
- Fix incorrect enable vs. disable power well call in
skl_display_core_uninit() (Patrik)
- Add commit comment about chaning the order of PW1 and Misc IO power
well disabling (Patrik)
CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1459773777-10701-1-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
0 files changed, 0 insertions, 0 deletions