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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-10-16 20:52:32 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-10-24 16:34:11 +0200 |
| commit | 142d2eca356af6744c7e4bb577c3dfaadee486fc (patch) | |
| tree | 743a2c3a551483bf5908e849631aa921f30bc29d /drivers/gpu/drm/i915/intel_dp_mst.c | |
| parent | 0039a4b357477bd8bcd495e4160974c71657b3e6 (diff) | |
| download | linux-142d2eca356af6744c7e4bb577c3dfaadee486fc.tar.gz linux-142d2eca356af6744c7e4bb577c3dfaadee486fc.tar.bz2 linux-142d2eca356af6744c7e4bb577c3dfaadee486fc.zip | |
drm/i915: Fix chv PCS DW11 register defines
I managed to fumble the per spline PCS DW11 register defines in:
commit 570e2a747bc06cd8620662c5125ec2dc964c511b
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Mon Aug 18 14:42:46 2014 +0300
drm/i915: Clear TX FIFO reset master override bits on chv
Fortunately the bit in DW0 that was cleared due to this didn't have
any effect as long as the bit we meant to clear was already zero.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Fix commit ref as pointed out by Jani.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions