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| author | Michal Wajdeczko <michal.wajdeczko@intel.com> | 2017-10-16 14:47:13 +0000 |
|---|---|---|
| committer | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2017-10-16 18:53:24 +0300 |
| commit | d9e2e0143cee8a3c08ce7db4e3adc6aebc84d1ed (patch) | |
| tree | 4086894f408dccc9b1b01500ce23d41aa39e1cbf /drivers/gpu/drm/i915/intel_guc.h | |
| parent | fdc6d7319e2b2da9ac108691c2039ee836779222 (diff) | |
| download | linux-d9e2e0143cee8a3c08ce7db4e3adc6aebc84d1ed.tar.gz linux-d9e2e0143cee8a3c08ce7db4e3adc6aebc84d1ed.tar.bz2 linux-d9e2e0143cee8a3c08ce7db4e3adc6aebc84d1ed.zip | |
drm/i915/guc: Move doc near related definitions
After GuC code reorg some documentation was left in wrong
place. Move it closer to corresponding definitions.
v2: use consistent name for the GuC (Sagar)
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171016144724.17244-5-michal.wajdeczko@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_guc.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_guc.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 8b441650e64b..9ad59645b7fe 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -33,6 +33,11 @@ #include "i915_guc_reg.h" #include "i915_vma.h" +/* + * Top level structure of GuC. It handles firmware loading and manages client + * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy + * ExecList submission. + */ struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; @@ -83,6 +88,12 @@ static inline void intel_guc_notify(struct intel_guc *guc) guc->notify(guc); } +/* + * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), + * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is + * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects + * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. + */ static inline u32 guc_ggtt_offset(struct i915_vma *vma) { u32 offset = i915_ggtt_offset(vma); |