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authorRoy Spliet <r.spliet@student.tudelft.nl>2012-01-09 15:23:07 +1000
committerBen Skeggs <bskeggs@redhat.com>2012-03-13 17:07:50 +1000
commitc7c039fd31be82ecb8d48477955e76badd38141a (patch)
tree0b527eba7fd021ce99c52d9f744d503d0919849c /drivers/gpu/drm/nouveau/nv50_vram.c
parent03ddf04bdb9cc4cdf8edb231b78f031647498314 (diff)
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drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation
Roy Spliet: - Implement according to specs - Simplify - Make array for mc latency registers Martin Peres: - squash and split all the commits from Roy - rework following Ben Skeggs comments - add a form of timings validation - store the initial timings for later use Ben Skeggs - merge slightly modified tidy-up patch with this one - remove perflvl-dropping logic for the moment Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_vram.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_vram.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_vram.c b/drivers/gpu/drm/nouveau/nv50_vram.c
index 1467efc6d61d..a52b9a51e010 100644
--- a/drivers/gpu/drm/nouveau/nv50_vram.c
+++ b/drivers/gpu/drm/nouveau/nv50_vram.c
@@ -207,6 +207,7 @@ nv50_vram_init(struct drm_device *dev)
break;
}
+ dev_priv->vram_rank_B = (nv_rd32(dev, NV04_PFB_CFG0) & 0x100) >> 8;
dev_priv->vram_size = nv_rd32(dev, 0x10020c);
dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
dev_priv->vram_size &= 0xffffffff00ULL;