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| author | Alex Deucher <alexdeucher@gmail.com> | 2010-02-04 11:01:52 -0500 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-02-09 09:32:24 +1000 |
| commit | 44224c3f455886190b101dbb00befbaff5e98466 (patch) | |
| tree | 51f618073d3c19a417fb707350846cfaa5f2813f /drivers/gpu/drm/radeon/r600_blit_kms.c | |
| parent | a0c07a69bc5d060362e4861d6c4f7c67dab57f1e (diff) | |
| download | linux-44224c3f455886190b101dbb00befbaff5e98466.tar.gz linux-44224c3f455886190b101dbb00befbaff5e98466.tar.bz2 linux-44224c3f455886190b101dbb00befbaff5e98466.zip | |
drm/radeon/kms/r600: reduce gpu cache flushing
Only flush the gpu caches before we submit a fence.
This leads to a small performance boost when we take
the extra gpu cache flushes out of the ddx and mesa.
Once this patch is in and the drm version is bumped,
we can remove the flushes from the ddx and drm.
Also, remove the extra cache flushes from the blit
routine.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_blit_kms.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600_blit_kms.c | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index af1c3ca8a4cb..2d7d16e14f9e 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c @@ -403,8 +403,6 @@ set_default_state(struct radeon_device *rdev) radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); radeon_ring_write(rdev, dwords); - radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); - radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); /* SQ config */ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); @@ -581,9 +579,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) ring_size = num_loops * dwords_per_loop; /* set default + shaders */ ring_size += 40; /* shaders + def state */ - ring_size += 7; /* fence emit for VB IB */ + ring_size += 12; /* fence emit for VB IB */ ring_size += 5; /* done copy */ - ring_size += 7; /* fence emit for done copy */ + ring_size += 12; /* fence emit for done copy */ r = radeon_ring_lock(rdev, ring_size); if (r) return r; @@ -597,13 +595,6 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) { int r; - radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); - radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); - /* wait for 3D idle clean */ - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); - radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); - radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); - if (rdev->r600_blit.vb_ib) r600_vb_ib_put(rdev); |