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| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2020-04-29 15:10:22 +0300 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2020-05-05 10:00:07 +0300 |
| commit | a8d9d7da1546349f18eb2d6b6b3a04bdeb38719d (patch) | |
| tree | 994eb3ae1eb103f7d67ee8187472ae49de0e992e /drivers/gpu/drm/tidss | |
| parent | 9cd39de4db54062ad60f8004362c293c0c950456 (diff) | |
| download | linux-a8d9d7da1546349f18eb2d6b6b3a04bdeb38719d.tar.gz linux-a8d9d7da1546349f18eb2d6b6b3a04bdeb38719d.tar.bz2 linux-a8d9d7da1546349f18eb2d6b6b3a04bdeb38719d.zip | |
drm/tidss: remove AM65x PG1 YUV erratum code
AM65x PG1 has a HW issue with YUV pixel formats, resulting in wrong
colors on the screen. This issue is fixed in PG2 hardware.
The driver currently has code to hide YUV pixel formats from the
userspace. To support PG2, we would need to add code to detect the SoC
version and hide the YUV formats based on that.
However, as PG1 will be phased out and PG2 will be the main platform, a
much simpler solution is just to drop the code in question. The downside
is that the users will be able to use YUV formats on PG1, getting wrong
colors on the screen. On the other hand, that may also be a plus, as the
same applications will now work on PG1 and PG2, even if the colors are
wrong on PG1.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200429121022.3871-1-tomi.valkeinen@ti.com
Reviewed-by: Jyri Sarha <jsarha@ti.com>
Diffstat (limited to 'drivers/gpu/drm/tidss')
| -rw-r--r-- | drivers/gpu/drm/tidss/tidss_dispc.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/drm/tidss/tidss_dispc.h | 6 |
2 files changed, 2 insertions, 15 deletions
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 29f42768e294..629dd06393f6 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -181,10 +181,6 @@ const struct dispc_features dispc_am65x_feats = { .vid_name = { "vid", "vidl1" }, .vid_lite = { false, true, }, .vid_order = { 1, 0 }, - - .errata = { - .i2000 = true, - }, }; static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { @@ -2674,12 +2670,9 @@ int dispc_init(struct tidss_device *tidss) return -ENOMEM; num_fourccs = 0; - for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { - if (feat->errata.i2000 && - dispc_fourcc_is_yuv(dispc_color_formats[i].fourcc)) - continue; + for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc; - } + dispc->num_fourccs = num_fourccs; dispc->tidss = tidss; dispc->dev = dev; diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h index a4a68249e44b..902e612ff7ac 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -46,10 +46,6 @@ struct dispc_features_scaling { u32 xinc_max; }; -struct dispc_errata { - bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */ -}; - enum dispc_vp_bus_type { DISPC_VP_DPI, /* DPI output */ DISPC_VP_OLDI, /* OLDI (LVDS) output */ @@ -83,8 +79,6 @@ struct dispc_features { const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */ bool vid_lite[TIDSS_MAX_PLANES]; u32 vid_order[TIDSS_MAX_PLANES]; - - struct dispc_errata errata; }; extern const struct dispc_features dispc_k2g_feats; |