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author | Jyri Sarha <jsarha@ti.com> | 2016-08-11 19:09:43 +0300 |
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committer | Jyri Sarha <jsarha@ti.com> | 2016-09-01 22:32:11 +0300 |
commit | bcc5a6f5fc9f0d53aa896768d6f86d7e64d0b783 (patch) | |
tree | d0c7baa4215b436456cae33d0550c5bb46db9019 /drivers/gpu/drm/tilcdc/tilcdc_drv.h | |
parent | 7eb9f069ff5dd39d44d7ecdf63eb99b429c7dad0 (diff) | |
download | linux-bcc5a6f5fc9f0d53aa896768d6f86d7e64d0b783.tar.gz linux-bcc5a6f5fc9f0d53aa896768d6f86d7e64d0b783.tar.bz2 linux-bcc5a6f5fc9f0d53aa896768d6f86d7e64d0b783.zip |
drm/tilcdc: Add blue-and-red-crossed devicetree property
Add "blue-and-red-wiring"-device tree property and update devicetree
binding document.
The red and blue components are reversed between 24 and 16 bit modes
on am335x LCDC output pins. To get 24 RGB format the red and blue
wires has to be crossed and this in turn causes 16 colors output to be
in BGR format. With straight wiring the 16 color is RGB and 24 bit is
BGR.
The new property describes whether the red and blue wires are crossed
or not. If the property is not present or its value is not recognized
the legacy mode is assumed. The legacy configuration supports RGB565,
RGB888 and XRGB8888 formats. However, depending on wiring, the red and
blue colors are swapped in either 16 or 24-bit color modes.
For more details see section 3.1.1 in AM335x Silicon Errata:
http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/tilcdc/tilcdc_drv.h')
-rw-r--r-- | drivers/gpu/drm/tilcdc/tilcdc_drv.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h b/drivers/gpu/drm/tilcdc/tilcdc_drv.h index 13001df7dbe8..0e19c1400386 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h @@ -65,6 +65,10 @@ struct tilcdc_drm_private { */ uint32_t max_width; + /* Supported pixel formats */ + const uint32_t *pixelformats; + uint32_t num_pixelformats; + /* The context for pm susped/resume cycle is stored here */ struct drm_atomic_state *saved_state; |