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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-05-27 10:26:43 +0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-05-28 11:17:26 -0700 |
| commit | a1786bd270b08834a735e06c3d5430eeb0baf017 (patch) | |
| tree | 72dd1d0482a341bfba0e3c3e967a9435c64ee95b /drivers/gpu | |
| parent | ca76482e0f4b64942c704fa11c620ffd1bdd8475 (diff) | |
| download | linux-a1786bd270b08834a735e06c3d5430eeb0baf017.tar.gz linux-a1786bd270b08834a735e06c3d5430eeb0baf017.tar.bz2 linux-a1786bd270b08834a735e06c3d5430eeb0baf017.zip | |
drm/i915: Unmask interrupt for render engine on Sandybridge
With splitted engines on Sandybridge, each engine has its own
interrupt control as well. This unmasks the interrupt to properly
enable pipe control notify event for render engine.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index af7b10853e33..64b0a3afd92b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -369,6 +369,25 @@ #define BB_ADDR 0x02140 /* 8 bytes */ #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ +/* GEN6 interrupt control */ +#define GEN6_RENDER_HWSTAM 0x2098 +#define GEN6_RENDER_IMR 0x20a8 +#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) +#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) +#define GEN6_RENDER TIMEOUT_COUNTER_EXPIRED (1 << 6) +#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) +#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) +#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) +#define GEN6_RENDER_SYNC_STATUS (1 << 2) +#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) +#define GEN6_RENDER_USER_INTERRUPT (1 << 0) + +#define GEN6_BLITTER_HWSTAM 0x22098 +#define GEN6_BLITTER_IMR 0x220a8 +#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) +#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) +#define GEN6_BLITTER_SYNC_STATUS (1 << 24) +#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) /* * BSD (bit stream decoder instruction and interrupt control register defines * (G4X and Ironlake only) |