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| author | Stefan Richter <stefanr@s5r6.in-berlin.de> | 2005-12-01 18:51:56 -0500 |
|---|---|---|
| committer | Jody McIntyre <scjody@modernduck.com> | 2005-12-01 18:51:56 -0500 |
| commit | d7758461b9a8253f1c125e5907579e0594d29e3b (patch) | |
| tree | 3273cf3f8a33dd962326d08cb6030e9c6d881f0b /drivers/ieee1394/ieee1394.h | |
| parent | 14c0fa243b358c24040ff5f44b60c47aaf6430c3 (diff) | |
| download | linux-d7758461b9a8253f1c125e5907579e0594d29e3b.tar.gz linux-d7758461b9a8253f1c125e5907579e0594d29e3b.tar.bz2 linux-d7758461b9a8253f1c125e5907579e0594d29e3b.zip | |
ieee1394: add definitions for phy packet constants
Introduce new macros related to phy packets and use them in ieee1394_core and
nodemgr.
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
Signed-off-by: Jody McIntyre <scjody@modernduck.com>
Diffstat (limited to 'drivers/ieee1394/ieee1394.h')
| -rw-r--r-- | drivers/ieee1394/ieee1394.h | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/drivers/ieee1394/ieee1394.h b/drivers/ieee1394/ieee1394.h index b634a9bb365c..936d776de00a 100644 --- a/drivers/ieee1394/ieee1394.h +++ b/drivers/ieee1394/ieee1394.h @@ -62,6 +62,7 @@ extern const char *hpsb_speedto_str[]; +/* 1394a cable PHY packets */ #define SELFID_PWRCL_NO_POWER 0x0 #define SELFID_PWRCL_PROVIDE_15W 0x1 #define SELFID_PWRCL_PROVIDE_30W 0x2 @@ -76,8 +77,24 @@ extern const char *hpsb_speedto_str[]; #define SELFID_PORT_NCONN 0x1 #define SELFID_PORT_NONE 0x0 +#define PHYPACKET_LINKON 0x40000000 +#define PHYPACKET_PHYCONFIG_R 0x00800000 +#define PHYPACKET_PHYCONFIG_T 0x00400000 +#define EXTPHYPACKET_TYPE_PING 0x00000000 +#define EXTPHYPACKET_TYPE_REMOTEACCESS_BASE 0x00040000 +#define EXTPHYPACKET_TYPE_REMOTEACCESS_PAGED 0x00140000 +#define EXTPHYPACKET_TYPE_REMOTEREPLY_BASE 0x000C0000 +#define EXTPHYPACKET_TYPE_REMOTEREPLY_PAGED 0x001C0000 +#define EXTPHYPACKET_TYPE_REMOTECOMMAND 0x00200000 +#define EXTPHYPACKET_TYPE_REMOTECONFIRMATION 0x00280000 +#define EXTPHYPACKET_TYPE_RESUME 0x003C0000 -/* 1394a PHY bitmasks */ +#define EXTPHYPACKET_TYPEMASK 0xC0FC0000 + +#define PHYPACKET_PORT_SHIFT 24 +#define PHYPACKET_GAPCOUNT_SHIFT 16 + +/* 1394a PHY register map bitmasks */ #define PHY_00_PHYSICAL_ID 0xFC #define PHY_00_R 0x02 /* Root */ #define PHY_00_PS 0x01 /* Power Status*/ |