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| author | Stefan Roscher <ossrosch@linux.vnet.ibm.com> | 2008-04-29 13:46:53 -0700 |
|---|---|---|
| committer | Roland Dreier <rolandd@cisco.com> | 2008-04-29 13:46:53 -0700 |
| commit | d227fa7288adebe5ba37fa8e4a589c977d4e4a34 (patch) | |
| tree | 8e0f080fc78f0342b5fd2531615ea525333d8d25 /drivers/infiniband/hw/ehca/ehca_classes.h | |
| parent | f56bcd8013566d4ad4759ae5fc85a6660e4655c7 (diff) | |
| download | linux-d227fa7288adebe5ba37fa8e4a589c977d4e4a34.tar.gz linux-d227fa7288adebe5ba37fa8e4a589c977d4e4a34.tar.bz2 linux-d227fa7288adebe5ba37fa8e4a589c977d4e4a34.zip | |
IB/ehca: Allocate event queue size depending on max number of CQs and QPs
If a lot of QPs fall into Error state at once and the EQ of the
respective HCA is too small, it might overrun, causing the eHCA driver
to stop processing completion events and calling the application's
completion handlers, effectively causing traffic to stop.
Fix this by limiting available QPs and CQs to a customizable max
count, and determining EQ size based on these counts and a worst-case
assumption.
Signed-off-by: Stefan Roscher <stefan.roscher@de.ibm.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/ehca/ehca_classes.h')
| -rw-r--r-- | drivers/infiniband/hw/ehca/ehca_classes.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/ehca/ehca_classes.h b/drivers/infiniband/hw/ehca/ehca_classes.h index 3d6d9461c31d..00bab60f6de4 100644 --- a/drivers/infiniband/hw/ehca/ehca_classes.h +++ b/drivers/infiniband/hw/ehca/ehca_classes.h @@ -66,6 +66,7 @@ struct ehca_av; #include "ehca_irq.h" #define EHCA_EQE_CACHE_SIZE 20 +#define EHCA_MAX_NUM_QUEUES 0xffff struct ehca_eqe_cache_entry { struct ehca_eqe *eqe; @@ -127,6 +128,8 @@ struct ehca_shca { /* MR pgsize: bit 0-3 means 4K, 64K, 1M, 16M respectively */ u32 hca_cap_mr_pgsize; int max_mtu; + atomic_t num_cqs; + atomic_t num_qps; }; struct ehca_pd { @@ -344,6 +347,8 @@ extern int ehca_use_hp_mr; extern int ehca_scaling_code; extern int ehca_lock_hcalls; extern int ehca_nr_ports; +extern int ehca_max_cq; +extern int ehca_max_qp; struct ipzu_queue_resp { u32 qe_size; /* queue entry size */ |