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author | Georgi Djakov <georgi.djakov@linaro.org> | 2019-01-16 18:10:56 +0200 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-01-22 13:37:25 +0100 |
commit | 11f1ceca7031deefc1a34236ab7b94360016b71d (patch) | |
tree | 36f1f8c883a4d268b8b9e5c55d0b22e85cda8a8e /drivers/interconnect/Kconfig | |
parent | 2ca46ed207d5d4e3c7a183fe11e8a2d02f86e7c6 (diff) | |
download | linux-11f1ceca7031deefc1a34236ab7b94360016b71d.tar.gz linux-11f1ceca7031deefc1a34236ab7b94360016b71d.tar.bz2 linux-11f1ceca7031deefc1a34236ab7b94360016b71d.zip |
interconnect: Add generic on-chip interconnect API
This patch introduces a new API to get requirements and configure the
interconnect buses across the entire chipset to fit with the current
demand.
The API is using a consumer/provider-based model, where the providers are
the interconnect buses and the consumers could be various drivers.
The consumers request interconnect resources (path) between endpoints and
set the desired constraints on this data flow path. The providers receive
requests from consumers and aggregate these requests for all master-slave
pairs on that path. Then the providers configure each node along the path
to support a bandwidth that satisfies all bandwidth requests that cross
through that node. The topology could be complicated and multi-tiered and
is SoC specific.
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/interconnect/Kconfig')
-rw-r--r-- | drivers/interconnect/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig new file mode 100644 index 000000000000..a261c7d41deb --- /dev/null +++ b/drivers/interconnect/Kconfig @@ -0,0 +1,10 @@ +menuconfig INTERCONNECT + tristate "On-Chip Interconnect management support" + help + Support for management of the on-chip interconnects. + + This framework is designed to provide a generic interface for + managing the interconnects in a SoC. + + If unsure, say no. + |