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authorYong Wu <yong.wu@mediatek.com>2017-08-21 19:00:16 +0800
committerJoerg Roedel <jroedel@suse.de>2017-08-22 16:37:58 +0200
commite6dec92308628cff5f1f8bd1bcdf87581c9dc676 (patch)
treed17007990ff95de3df378b2d6625f25e8b815b54 /drivers/iommu/mtk_iommu.h
parenta9467d954226f1a513cfe789a3a39d8fc73b5d16 (diff)
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iommu/mediatek: Add mt2712 IOMMU support
The M4U IP blocks in mt2712 is MTK's generation2 M4U which use the ARM Short-descriptor like mt8173, and most of the HW registers are the same. The difference is that there are 2 M4U HWs in mt2712 while there's only one in mt8173. The purpose of 2 M4U HWs is for balance the bandwidth. Normally if there are 2 M4U HWs, there should be 2 iommu domains, each M4U has a iommu domain. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu/mtk_iommu.h')
-rw-r--r--drivers/iommu/mtk_iommu.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index c06cc91b5d9a..462e593b7d71 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -34,6 +34,12 @@ struct mtk_iommu_suspend_reg {
u32 int_main_control;
};
+enum mtk_iommu_plat {
+ M4U_MT2701,
+ M4U_MT2712,
+ M4U_MT8173,
+};
+
struct mtk_iommu_domain;
struct mtk_iommu_data {
@@ -50,6 +56,7 @@ struct mtk_iommu_data {
bool tlb_flush_active;
struct iommu_device iommu;
+ enum mtk_iommu_plat m4u_plat;
};
static inline int compare_of(struct device *dev, void *data)