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| author | Kishon Vijay Abraham I <kishon@ti.com> | 2018-02-05 18:20:18 +0530 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2018-03-05 09:00:58 +0100 |
| commit | 7d33c3581536b8193b9788a63a68e7bfc22cdc31 (patch) | |
| tree | ea224e2cbeba8632970107ca2991ada4fe3ba3bf /drivers/mmc/host/sdhci-omap.c | |
| parent | 9fc2cd76125cab476ec6fd86fac7f9a780e34dcf (diff) | |
| download | linux-7d33c3581536b8193b9788a63a68e7bfc22cdc31.tar.gz linux-7d33c3581536b8193b9788a63a68e7bfc22cdc31.tar.bz2 linux-7d33c3581536b8193b9788a63a68e7bfc22cdc31.zip | |
mmc: sdhci-omap: Workaround for Errata i802
Errata i802 in AM572x Sitara Processors Silicon Revision 2.0, 1.1
(SPRZ429K July 2014–Revised March 2017 [1]) mentions
DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
during the tuning procedure and it has to be disabled during the
tuning procedure Implement workaround for Errata i802 here..
[1] -> http://www.ti.com/lit/er/sprz429k/sprz429k.pdf
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/sdhci-omap.c')
| -rw-r--r-- | drivers/mmc/host/sdhci-omap.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index 36e0626d3de2..e24ae903f7ba 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -257,6 +257,7 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) u32 start_window = 0, max_window = 0; u8 cur_match, prev_match = 0; u32 length = 0, max_len = 0; + u32 ier = host->ier; u32 phase_delay = 0; int ret = 0; u32 reg; @@ -277,6 +278,16 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) reg |= DLL_SWT; sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); + /* + * OMAP5/DRA74X/DRA72x Errata i802: + * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur + * during the tuning procedure. So disable it during the + * tuning procedure. + */ + ier &= ~SDHCI_INT_DATA_CRC; + sdhci_writel(host, ier, SDHCI_INT_ENABLE); + sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); + while (phase_delay <= MAX_PHASE_DELAY) { sdhci_omap_set_dll(omap_host, phase_delay); @@ -322,6 +333,8 @@ tuning_error: ret: sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); return ret; } |