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| author | Pierre Ossman <drzeus@drzeus.cx> | 2006-11-08 23:06:35 +0100 |
|---|---|---|
| committer | Pierre Ossman <drzeus@drzeus.cx> | 2006-12-01 18:54:10 +0100 |
| commit | 077df884835ebf2b5db16aacd9a24691d89902a0 (patch) | |
| tree | 6d812005b3f5c9062ccd8dd2157a558a9bb1f0ed /drivers/mmc/sdhci.h | |
| parent | 7ccd266e676a3f0c6f8f897f58b684cac3dd1650 (diff) | |
| download | linux-077df884835ebf2b5db16aacd9a24691d89902a0.tar.gz linux-077df884835ebf2b5db16aacd9a24691d89902a0.tar.bz2 linux-077df884835ebf2b5db16aacd9a24691d89902a0.zip | |
mmc: sdhci high speed support
The SDHCI spec implies that is is incorrect to set a clock
frequency above 25 MHz without setting the high speed bit.
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
Diffstat (limited to 'drivers/mmc/sdhci.h')
| -rw-r--r-- | drivers/mmc/sdhci.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mmc/sdhci.h b/drivers/mmc/sdhci.h index 72a67937afe0..f9d1a0a6f03a 100644 --- a/drivers/mmc/sdhci.h +++ b/drivers/mmc/sdhci.h @@ -71,6 +71,7 @@ #define SDHCI_HOST_CONTROL 0x28 #define SDHCI_CTRL_LED 0x01 #define SDHCI_CTRL_4BITBUS 0x02 +#define SDHCI_CTRL_HISPD 0x04 #define SDHCI_POWER_CONTROL 0x29 #define SDHCI_POWER_ON 0x01 @@ -138,6 +139,7 @@ #define SDHCI_CLOCK_BASE_SHIFT 8 #define SDHCI_MAX_BLOCK_MASK 0x00030000 #define SDHCI_MAX_BLOCK_SHIFT 16 +#define SDHCI_CAN_DO_HISPD 0x00200000 #define SDHCI_CAN_DO_DMA 0x00400000 #define SDHCI_CAN_VDD_330 0x01000000 #define SDHCI_CAN_VDD_300 0x02000000 |