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authorMasahiro Yamada <yamada.masahiro@socionext.com>2017-02-14 20:05:40 +0900
committerUlf Hansson <ulf.hansson@linaro.org>2017-02-15 11:32:14 +0100
commit4e03f628b464e0580abadf5161eaa38c61d20943 (patch)
tree6d929f2c69d9bd4f725c2bb3266e2400d1b8224e /drivers/mmc
parent006cac8262987981fb10a0360726875b48123b73 (diff)
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mmc: sdhci-cadence: fix bit shift of read data from PHY port
This macro is currently unused, but it may be useful for debug use. Fix it just in case. Fixes: ff6af28faff5 ("mmc: sdhci-cadence: add Cadence SD4HC support") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci-cadence.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 31e786d1b71a..316cfec3f005 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -26,7 +26,7 @@
#define SDHCI_CDNS_HRS04_ACK BIT(26)
#define SDHCI_CDNS_HRS04_RD BIT(25)
#define SDHCI_CDNS_HRS04_WR BIT(24)
-#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12
+#define SDHCI_CDNS_HRS04_RDATA_SHIFT 16
#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0