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authorAlexander Duyck <alexander.h.duyck@intel.com>2008-11-14 06:54:36 +0000
committerDavid S. Miller <davem@davemloft.net>2008-11-16 19:09:43 -0800
commit6ea7ae1d0fc02a6c4ccd27e43346f67c44226e7a (patch)
treecb07bd55c0d908cae9e3539dda6fa1c5bf6512f4 /drivers/net/e1000e/defines.h
parentf004f3ea34209d8b836426b26ade3dc502631b18 (diff)
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e1000e: enable ECC correction on 82571 silicon
This change enables ECC correction for the packet buffer on all 82571 silicon. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e/defines.h')
-rw-r--r--drivers/net/e1000e/defines.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h
index 48f79ecb82a0..34a68fcab5a9 100644
--- a/drivers/net/e1000e/defines.h
+++ b/drivers/net/e1000e/defines.h
@@ -372,6 +372,13 @@
#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
+/* PBA ECC Register */
+#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
+#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
+#define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */
+#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
+#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */
+
/*
* This defines the bits that are set in the Interrupt Mask
* Set/Read Register. Each bit is documented below: