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| author | Anish Bhatt <anish@chelsio.com> | 2014-08-07 16:14:03 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-08-07 16:18:55 -0700 |
| commit | 10b0046685ab410847f420d740acf604c8cb4eec (patch) | |
| tree | 9701e13839a8cb4289eb6fbf404373f5b39009e0 /drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h | |
| parent | a1f7d81b735cdd682b0e7c81bb2c6821cbbf8060 (diff) | |
| download | linux-10b0046685ab410847f420d740acf604c8cb4eec.tar.gz linux-10b0046685ab410847f420d740acf604c8cb4eec.tar.bz2 linux-10b0046685ab410847f420d740acf604c8cb4eec.zip | |
cxgb4: IEEE fixes for DCBx state machine
* Changes required due to 16eecd9be4b05 ("dcbnl : Fix misleading
dcb_app->priority explanation")
* Driver was previously not aware of what DCBx version was negotiated by
firmware, this could lead to DCB app table in kernel or in firmware being
populated wrong since IEEE/CEE used different formats made clear by above
mentioned commit
* Driver was missing a couple of state transitions that could be caused
by other drivers that use chelsio hardware, resulting in incorrect behaviour
(the change that addresses this also flips the state machine to switch on
state instead of transition, hope this is okay in current window)
* Prio queue info & tsa is no longer thrown away
v2: Print DCBx state transition messages only when debug is enabled
Signed-off-by: Anish Bhatt <anish@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h')
| -rw-r--r-- | drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h index ff709e3b3e7e..0549170d7e2e 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h +++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h @@ -1629,6 +1629,14 @@ enum fw_port_l2cfg_ctlbf { FW_PORT_L2_CTLBF_TXIPG = 0x20 }; +enum fw_port_dcb_versions { + FW_PORT_DCB_VER_UNKNOWN, + FW_PORT_DCB_VER_CEE1D0, + FW_PORT_DCB_VER_CEE1D01, + FW_PORT_DCB_VER_IEEE, + FW_PORT_DCB_VER_AUTO = 7 +}; + enum fw_port_dcb_cfg { FW_PORT_DCB_CFG_PG = 0x01, FW_PORT_DCB_CFG_PFC = 0x02, @@ -1709,6 +1717,7 @@ struct fw_port_cmd { __u8 r10_lo[5]; __u8 num_tcs_supported; __u8 pgrate[8]; + __u8 tsa[8]; } pgrate; struct fw_port_dcb_priorate { __u8 type; @@ -1735,7 +1744,7 @@ struct fw_port_cmd { struct fw_port_dcb_control { __u8 type; __u8 all_syncd_pkd; - __be16 pfc_state_to_app_state; + __be16 dcb_version_to_app_state; __be32 r11; __be64 r12; } control; @@ -1778,6 +1787,7 @@ struct fw_port_cmd { #define FW_PORT_CMD_DCBXDIS (1U << 7) #define FW_PORT_CMD_APPLY (1U << 7) #define FW_PORT_CMD_ALL_SYNCD (1U << 7) +#define FW_PORT_CMD_DCB_VERSION_GET(x) (((x) >> 8) & 0xf) #define FW_PORT_CMD_PPPEN(x) ((x) << 31) #define FW_PORT_CMD_TPSRC(x) ((x) << 28) |