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authorSathya Perla <sathya.perla@emulex.com>2012-11-06 17:48:59 +0000
committerDavid S. Miller <davem@davemloft.net>2012-11-07 16:59:52 -0500
commit1bc8e7e4f36c0c19dd7dea29e7c248b7c6ef3a15 (patch)
tree510d8b113fa050d595480054aea7759dbecfe43c /drivers/net/ethernet/emulex/benet/be_hw.h
parentce66f781cff6b3522b1234096db77e8bacdbf3c3 (diff)
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be2net: fix access to SEMAPHORE reg
The SEMAPHORE register was being accessed from the csr BAR space. This BAR may not be available in some Skyhawk-R configurations. Instead, access this register via the PCI config space (it's available there too). Signed-off-by: Sathya Perla <sathya.perla@emulex.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/emulex/benet/be_hw.h')
-rw-r--r--drivers/net/ethernet/emulex/benet/be_hw.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/net/ethernet/emulex/benet/be_hw.h b/drivers/net/ethernet/emulex/benet/be_hw.h
index c25720760173..541d4530d5bf 100644
--- a/drivers/net/ethernet/emulex/benet/be_hw.h
+++ b/drivers/net/ethernet/emulex/benet/be_hw.h
@@ -31,12 +31,12 @@
#define MPU_EP_CONTROL 0
-/********** MPU semphore ******************/
-#define MPU_EP_SEMAPHORE_OFFSET 0xac
-#define MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET 0x400
-#define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
-#define EP_SEMAPHORE_POST_ERR_MASK 0x1
-#define EP_SEMAPHORE_POST_ERR_SHIFT 31
+/********** MPU semphore: used for SH & BE *************/
+#define SLIPORT_SEMAPHORE_OFFSET_BE 0x7c
+#define SLIPORT_SEMAPHORE_OFFSET_SH 0x94
+#define POST_STAGE_MASK 0x0000FFFF
+#define POST_ERR_MASK 0x1
+#define POST_ERR_SHIFT 31
/* MPU semphore POST stage values */
#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */