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| author | Geetha sowjanya <gakula@marvell.com> | 2018-10-16 16:57:14 +0530 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-10-17 21:33:43 -0700 |
| commit | 57856dde119590462315ddb5b4bf5fd2d981cb36 (patch) | |
| tree | f645e5ce03d9361950ca9589aac7088226f0eded /drivers/net/ethernet/marvell/octeontx2/af/mbox.h | |
| parent | 4a3581cd5995d86721b3a38e1e2799b2137b4d77 (diff) | |
| download | linux-57856dde119590462315ddb5b4bf5fd2d981cb36.tar.gz linux-57856dde119590462315ddb5b4bf5fd2d981cb36.tar.bz2 linux-57856dde119590462315ddb5b4bf5fd2d981cb36.zip | |
octeontx2-af: Support for disabling NPA Aura/Pool contexts
This patch adds support for a RVU PF/VF to disable all Aura/Pool
contexts of a NPA LF via mbox. This will be used by PF/VF drivers
upon teardown or while freeing up HW resources.
A HW context which is not INIT'ed cannot be modified and a
RVU PF/VF driver may or may not INIT all the Aura/Pool contexts.
So a bitmap is introduced to keep track of enabled NPA Aura/Pool
contexts, so that only enabled hw contexts are disabled upon LF
teardown.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Stanislaw Kardach <skardach@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/mbox.h')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h index bf11058ac30c..4e873147538d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -142,6 +142,7 @@ M(CGX_INTLBK_DISABLE, 0x20B, msg_req, msg_rsp) \ M(NPA_LF_ALLOC, 0x400, npa_lf_alloc_req, npa_lf_alloc_rsp) \ M(NPA_LF_FREE, 0x401, msg_req, msg_rsp) \ M(NPA_AQ_ENQ, 0x402, npa_aq_enq_req, npa_aq_enq_rsp) \ +M(NPA_HWCTX_DISABLE, 0x403, hwctx_disable_req, msg_rsp) \ /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ @@ -325,4 +326,10 @@ struct npa_aq_enq_rsp { }; }; +/* Disable all contexts of type 'ctype' */ +struct hwctx_disable_req { + struct mbox_msghdr hdr; + u8 ctype; +}; + #endif /* MBOX_H */ |