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| author | Niklas Cassel <niklas.cassel@axis.com> | 2016-11-24 15:36:33 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-11-29 19:10:47 -0500 |
| commit | 436feafe95cc2de3e1a56a0679c80291e1776894 (patch) | |
| tree | 1beb1890773e1958ae1c312dbd0f97d517eb4090 /drivers/net/ethernet/stmicro/stmmac/dwmac4.h | |
| parent | 530742e707190b585f0874876ad1fcac9a0abbcb (diff) | |
| download | linux-436feafe95cc2de3e1a56a0679c80291e1776894.tar.gz linux-436feafe95cc2de3e1a56a0679c80291e1776894.tar.bz2 linux-436feafe95cc2de3e1a56a0679c80291e1776894.zip | |
net: stmmac: enable tx queue 0 for gmac4 IPs synthesized with multiple TX queues
The dwmac4 IP can synthesized with 1-8 number of tx queues.
On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled
by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0. The write will have no effect on IPs synthesized
with DWC_EQOS_NUM_TXQ == 1.
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/dwmac4.h')
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index 6f4f5ce25114..3e8d4fefa5e0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -155,8 +155,11 @@ enum power_event { #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38) #define MTL_OP_MODE_RSF BIT(5) +#define MTL_OP_MODE_TXQEN BIT(3) #define MTL_OP_MODE_TSF BIT(1) +#define MTL_OP_MODE_TQS_MASK GENMASK(24, 16) + #define MTL_OP_MODE_TTC_MASK 0x70 #define MTL_OP_MODE_TTC_SHIFT 4 |