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| author | Rajkumar Manoharan <rmanohar@qca.qualcomm.com> | 2011-11-22 18:52:00 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-11-28 14:36:22 -0500 |
| commit | a261f0e965b7e903873880cec1a70c9cbc776c76 (patch) | |
| tree | a97b242f5c58bdd7be622ea72d21cbaa3fb2fa3f /drivers/net/wireless/ath/ath9k/eeprom_9287.c | |
| parent | 4eb287a4048e4a2cb0400a6d972d97739ec8c799 (diff) | |
| download | linux-a261f0e965b7e903873880cec1a70c9cbc776c76.tar.gz linux-a261f0e965b7e903873880cec1a70c9cbc776c76.tar.bz2 linux-a261f0e965b7e903873880cec1a70c9cbc776c76.zip | |
ath9k_hw: Fix minimum CTL power for each runtime mode
The conformance test limits (CTL) for each regulatory domains
(FCC/ETSI/MKK) are programmed for each runtime modes (11B,11G,
HT20 and HT40) in EEPROM. The lowest ctledge power value of a
particular running mode should not be used while computing
ctledge power for a different running mode.(i.e 11G's min ctledge
power should not be used while computing ctledge power for HT20).
Currently, the code does not handle this properly which would
result in incorrect txpowers in certain cases. So reset the
twiceMaxEdgePower to the default while computing min ctlegepower
for every mode.
Cc: David Quan <dquan@qca.qualcomm.com>
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/eeprom_9287.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/eeprom_9287.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c index 4f5c50a87ce3..0981c073471d 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c @@ -569,7 +569,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 - u16 twiceMaxEdgePower = MAX_RATE_POWER; + u16 twiceMaxEdgePower; int i; struct cal_ctl_data_ar9287 *rep; struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} }, @@ -669,6 +669,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, else freq = centers.ctl_center; + twiceMaxEdgePower = MAX_RATE_POWER; /* Walk through the CTL indices stored in EEPROM */ for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { struct cal_ctl_edges *pRdEdgesPower; |