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| author | Avinash Patil <patila@marvell.com> | 2014-09-12 20:08:49 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2014-09-15 15:00:51 -0400 |
| commit | 2703a66865eb3a5b422749281371e9eefa8658c4 (patch) | |
| tree | a86bf52e45edd8bb9529b67135e0a93c37385092 /drivers/net/wireless/mwifiex | |
| parent | 3223db2086c987d4527fdaa487a027b0148e9692 (diff) | |
| download | linux-2703a66865eb3a5b422749281371e9eefa8658c4.tar.gz linux-2703a66865eb3a5b422749281371e9eefa8658c4.tar.bz2 linux-2703a66865eb3a5b422749281371e9eefa8658c4.zip | |
mwifiex: support for event done interrupt
This patch adds support for writing CPU event interrupt done back
to device.
Patch also increases interrupt buffer ring size from 4 to 8.
Signed-off-by: Avinash Patil <patila@marvell.com>
Signed-off-by: Cathy Luo <cluo@marvell.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/mwifiex')
| -rw-r--r-- | drivers/net/wireless/mwifiex/pcie.c | 7 | ||||
| -rw-r--r-- | drivers/net/wireless/mwifiex/pcie.h | 5 |
2 files changed, 10 insertions, 2 deletions
diff --git a/drivers/net/wireless/mwifiex/pcie.c b/drivers/net/wireless/mwifiex/pcie.c index 27c2bf860709..2ada1b709778 100644 --- a/drivers/net/wireless/mwifiex/pcie.c +++ b/drivers/net/wireless/mwifiex/pcie.c @@ -1726,6 +1726,13 @@ static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter) buffer is released. This is just to make things simpler, we need to find a better method of managing these buffers. */ + } else { + if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, + CPU_INTR_EVENT_DONE)) { + dev_warn(adapter->dev, + "Write register failed\n"); + return -1; + } } return 0; diff --git a/drivers/net/wireless/mwifiex/pcie.h b/drivers/net/wireless/mwifiex/pcie.h index a1a8fd3bc1be..200e8b0cb582 100644 --- a/drivers/net/wireless/mwifiex/pcie.h +++ b/drivers/net/wireless/mwifiex/pcie.h @@ -40,8 +40,8 @@ #define MWIFIEX_TXBD_MASK 0x3F #define MWIFIEX_RXBD_MASK 0x3F -#define MWIFIEX_MAX_EVT_BD 0x04 -#define MWIFIEX_EVTBD_MASK 0x07 +#define MWIFIEX_MAX_EVT_BD 0x08 +#define MWIFIEX_EVTBD_MASK 0x0f /* PCIE INTERNAL REGISTERS */ #define PCIE_SCRATCH_0_REG 0xC10 @@ -69,6 +69,7 @@ #define CPU_INTR_DOOR_BELL BIT(1) #define CPU_INTR_SLEEP_CFM_DONE BIT(2) #define CPU_INTR_RESET BIT(3) +#define CPU_INTR_EVENT_DONE BIT(5) #define HOST_INTR_DNLD_DONE BIT(0) #define HOST_INTR_UPLD_RDY BIT(1) |