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| author | Michael Chan <mchan@broadcom.com> | 2007-10-15 02:12:26 -0700 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2007-10-15 12:26:38 -0700 |
| commit | 114342f2d38439cb1a54f1f724fa38729b093c48 (patch) | |
| tree | 890694d32845ac75e7e7cbf80358d4e256e5d078 /drivers/net | |
| parent | faca94ffaed31528e2e859ee3c26d7d4dba6702f (diff) | |
| download | linux-114342f2d38439cb1a54f1f724fa38729b093c48.tar.gz linux-114342f2d38439cb1a54f1f724fa38729b093c48.tar.bz2 linux-114342f2d38439cb1a54f1f724fa38729b093c48.zip | |
[TG3]: Fix performance regression on 5705.
A performance regression was introduced by the following commit:
commit ee6a99b539a50b4e9398938a0a6d37f8bf911550
Author: Michael Chan <mchan@broadcom.com>
Date: Wed Jul 18 21:49:10 2007 -0700
[TG3]: Fix msi issue with kexec/kdump.
In making that change, the PCI latency timer and cache line size
registers were not restored after chip reset. On the 5705, the
latency timer gets reset to 0 during chip reset and this causes
very poor performance.
Update version to 3.84.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/tg3.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 30b1cca8144c..b9e1dc662363 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -64,8 +64,8 @@ #define DRV_MODULE_NAME "tg3" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "3.83" -#define DRV_MODULE_RELDATE "October 10, 2007" +#define DRV_MODULE_VERSION "3.84" +#define DRV_MODULE_RELDATE "October 12, 2007" #define TG3_DEF_MAC_MODE 0 #define TG3_DEF_RX_MODE 0 @@ -5056,6 +5056,12 @@ static void tg3_restore_pci_state(struct tg3 *tp) pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd); + if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { + pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, + tp->pci_cacheline_sz); + pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, + tp->pci_lat_timer); + } /* Make sure PCI-X relaxed ordering bit is clear. */ if (tp->pcix_cap) { u16 pcix_cmd; |