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| author | Mark Rutland <mark.rutland@arm.com> | 2023-12-04 11:58:47 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2023-12-05 12:34:24 +0000 |
| commit | ca6f537e459e2da4b331fe8928d1a0b0f9301f42 (patch) | |
| tree | 0b3bfcf33c5f00f7b0255e265b26348508625a11 /drivers/perf/arm_pmuv3.c | |
| parent | 877806b9b41ea371defaaf58d815320f1a76384f (diff) | |
| download | linux-ca6f537e459e2da4b331fe8928d1a0b0f9301f42.tar.gz linux-ca6f537e459e2da4b331fe8928d1a0b0f9301f42.tar.bz2 linux-ca6f537e459e2da4b331fe8928d1a0b0f9301f42.zip | |
drivers/perf: pmuv3: don't expose SW_INCR event in sysfs
The SW_INCR event is somewhat unusual, and depends on the specific HW
counter that it is programmed into. When programmed into PMEVCNTR<n>,
SW_INCR will count any writes to PMSWINC_EL0 with bit n set, ignoring
writes to SW_INCR with bit n clear.
Event rotation means that there's no fixed relationship between
perf_events and HW counters, so this isn't all that useful.
Further, we program PMUSERENR.{SW,EN}=={0,0}, which causes EL0 writes to
PMSWINC_EL0 to be trapped and handled as UNDEFINED, resulting in a
SIGILL to userspace.
Given that, it's not a good idea to expose SW_INCR in sysfs. Hide it as
we did for CHAIN back in commit:
4ba2578fa7b55701 ("arm64: perf: don't expose CHAIN event in sysfs")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20231204115847.2993026-1-mark.rutland@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/perf/arm_pmuv3.c')
| -rw-r--r-- | drivers/perf/arm_pmuv3.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index c136a6529014..bbde60f1b08c 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -169,7 +169,11 @@ armv8pmu_events_sysfs_show(struct device *dev, PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config) static struct attribute *armv8_pmuv3_event_attrs[] = { - ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR), + /* + * Don't expose the sw_incr event in /sys. It's not usable as writes to + * PMSWINC_EL0 will trap as PMUSERENR.{SW,EN}=={0,0} and event rotation + * means we don't have a fixed event<->counter relationship regardless. + */ ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL), ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL), ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL), |