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| author | Guillaume Ranquet <granquet@baylibre.com> | 2023-04-14 18:07:47 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-05-04 23:12:11 +0530 |
| commit | 9d9ff3d2a4a567b543b71c2967d2ccc5e0ac6816 (patch) | |
| tree | 9f14465942677067fa902f9e0894dea41db96635 /drivers/phy/mediatek | |
| parent | 714dd3c29a2241fb799586a5b03773103ca50fe5 (diff) | |
| download | linux-9d9ff3d2a4a567b543b71c2967d2ccc5e0ac6816.tar.gz linux-9d9ff3d2a4a567b543b71c2967d2ccc5e0ac6816.tar.bz2 linux-9d9ff3d2a4a567b543b71c2967d2ccc5e0ac6816.zip | |
phy: mediatek: hdmi: mt8195: fix wrong pll calculus
The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has
been replaced by 'div_u64'.
Fix the issue by multiplying the values in the denominator instead of
dividing them.
Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Link: https://lore.kernel.org/r/20230413-fixes-for-mt8195-hdmi-phy-v2-2-bbad62e64321@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/mediatek')
| -rw-r--r-- | drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c index 054b73cb31ee..caa953780bee 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -271,7 +271,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, * [32,24] 9bit integer, [23,0]:24bit fraction */ pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, - da_hdmitx21_ref_ck / PLL_FBKDIV_HS3); + da_hdmitx21_ref_ck * PLL_FBKDIV_HS3); if (pcw > GENMASK_ULL(32, 0)) return -EINVAL; @@ -288,7 +288,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, posdiv2 = 1; /* Digital clk divider, max /32 */ - digital_div = div_u64((u64)ns_hdmipll_ck, posdiv1 / posdiv2 / pixel_clk); + digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); if (!(digital_div <= 32 && digital_div >= 1)) return -EINVAL; |