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authorKishon Vijay Abraham I <kishon@ti.com>2014-06-25 23:22:57 +0530
committerKishon Vijay Abraham I <kishon@ti.com>2014-07-22 12:46:10 +0530
commitf0e2cf7b912522c9c7146d9d6e99d1b0ea5c97c6 (patch)
tree61081c79d550c40df4aa0f684e198c72eb4784d5 /drivers/phy/phy-ti-pipe3.c
parent99bbd48c2065552fd2d224c9f065dcac9b7e25ce (diff)
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phy: pipe3: insert delay to enumerate in GEN2 mode
8-bit delay value (0xF1) is required for GEN2 devices to be enumerated consistently. Added an API to be called from PHY drivers to set this delay value and called it from PIPE3 driver to set the delay value. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com>
Diffstat (limited to 'drivers/phy/phy-ti-pipe3.c')
-rw-r--r--drivers/phy/phy-ti-pipe3.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 6174f4b1a5de..93bcd67f1b22 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -217,8 +217,10 @@ static int ti_pipe3_init(struct phy *x)
u32 val;
int ret = 0;
- if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
+ if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
+ omap_control_pcie_pcs(phy->control_dev, phy->id, 0xF1);
return 0;
+ }
/* Bring it out of IDLE if it is IDLE */
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);