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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-11-14 21:53:03 +0100 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2016-11-15 10:23:02 +0100 |
| commit | 7c926492d38a3feef4b4b29c91b7c03eb1b8b546 (patch) | |
| tree | dc8f3376d7b16c7c424517e25d639fddd8230400 /drivers/pinctrl/intel | |
| parent | 51814827190214986c452a166718bf12d32211c7 (diff) | |
| download | linux-7c926492d38a3feef4b4b29c91b7c03eb1b8b546.tar.gz linux-7c926492d38a3feef4b4b29c91b7c03eb1b8b546.tar.bz2 linux-7c926492d38a3feef4b4b29c91b7c03eb1b8b546.zip | |
pinctrl: sunxi: Add support for interrupt debouncing
The pin controller found in the Allwinner SoCs has support for interrupts
debouncing.
However, this is not done per-pin, preventing us from using the generic
pinconf binding for that, but per irq bank, which, depending on the SoC,
ranges from one to five.
Introduce a device-wide property to deal with this using a microsecond
resolution. We can re-use the per-pin input-debounce property for that, so
let's do it!
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/intel')
0 files changed, 0 insertions, 0 deletions