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| author | Pritesh Raithatha <praithatha@nvidia.com> | 2013-01-08 13:02:36 +0530 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2013-01-18 16:13:52 +0100 |
| commit | 348d1bf75c09f854630e9bd161dc2a88aebe2149 (patch) | |
| tree | b7f3fd0f286d8191584c8d2f0200a29121e1acf2 /drivers/pinctrl/pinctrl-tegra20.c | |
| parent | b2083062a3b4035e85349120b426ecef2b6d155f (diff) | |
| download | linux-348d1bf75c09f854630e9bd161dc2a88aebe2149.tar.gz linux-348d1bf75c09f854630e9bd161dc2a88aebe2149.tar.bz2 linux-348d1bf75c09f854630e9bd161dc2a88aebe2149.zip | |
pinctrl: tegra: add support for rcv-sel and drive type
NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e.
rcv-sel and drive type.
rcv-sel: Select between High and Normal VIL/VIH receivers.
RCVR_SEL=1: High VIL/VIH
RCVR_SEL=0: Normal VIL/VIH
drv_type: Ouptput drive type:
33-50 ohm driver: 0x1
66-100ohm driver: 0x0
Add support of these parameters to be configure from DTS file.
Tegra20 and Tegra30 does not support this configuration and hence initialize their
pinmux structure with reg = -1.
Originally written by Pritesh Raithatha.
Changes by ldewangan:
- remove drvtype_width as it is always 2.
- Better describe the change.
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-tegra20.c')
| -rw-r--r-- | drivers/pinctrl/pinctrl-tegra20.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c index e848189038f0..fcfb7d012c5b 100644 --- a/drivers/pinctrl/pinctrl-tegra20.c +++ b/drivers/pinctrl/pinctrl-tegra20.c @@ -2624,7 +2624,9 @@ static const struct tegra_function tegra20_functions[] = { .odrain_reg = -1, \ .lock_reg = -1, \ .ioreset_reg = -1, \ + .rcv_sel_reg = -1, \ .drv_reg = -1, \ + .drvtype_reg = -1, \ } /* Pin groups with only pull up and pull down control */ @@ -2642,7 +2644,9 @@ static const struct tegra_function tegra20_functions[] = { .odrain_reg = -1, \ .lock_reg = -1, \ .ioreset_reg = -1, \ + .rcv_sel_reg = -1, \ .drv_reg = -1, \ + .drvtype_reg = -1, \ } /* Pin groups for drive strength registers (configurable version) */ @@ -2660,6 +2664,7 @@ static const struct tegra_function tegra20_functions[] = { .odrain_reg = -1, \ .lock_reg = -1, \ .ioreset_reg = -1, \ + .rcv_sel_reg = -1, \ .drv_reg = ((r) - PINGROUP_REG_A), \ .drv_bank = 3, \ .hsm_bit = hsm_b, \ @@ -2673,6 +2678,7 @@ static const struct tegra_function tegra20_functions[] = { .slwr_width = slwr_w, \ .slwf_bit = slwf_b, \ .slwf_width = slwf_w, \ + .drvtype_reg = -1, \ } /* Pin groups for drive strength registers (simple version) */ |