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authorZhi Mao <zhi.mao@mediatek.com>2017-06-30 14:05:17 +0800
committerThierry Reding <thierry.reding@gmail.com>2017-08-21 10:39:09 +0200
commitcd30798a6c17c1fa182e9b0bb85bd973776ff193 (patch)
tree3572bfe3bb23753643c6355852481c36e89c39bb /drivers/pwm
parentaa12d7a7a978ac5f3202cac8f2f671fd267bf5e3 (diff)
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pwm: mediatek: Fix PWM source clock selection
In original code, the PWM output frequency is not correct when set bit<3>=1 to PWMCON register. Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: John Crispin <john@phrozen.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm')
-rw-r--r--drivers/pwm/pwm-mediatek.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 5c11bc708a3c..d08b5b3dca71 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
if (clkdiv > 7)
return -EINVAL;
- mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
+ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);