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authorGeert Uytterhoeven <geert+renesas@glider.be>2016-06-28 16:10:34 +0200
committerSimon Horman <horms+renesas@verge.net.au>2016-06-29 14:37:24 +0200
commitced42730d19dd140a76f86c3761f646b83a35d09 (patch)
tree076463d68b8178a53060c8372a2be4186f52e024 /drivers/soc
parent053239987f89f9a6299e78610bad010764bccd71 (diff)
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soc: renesas: rcar-sysc: Improve SYSC interrupt config in legacy wrapper
Align SYSC interrupt configuration in the legacy wrapper with the DT version: - Mask SYSC interrupt sources before enabling them (doesn't matter much as they're disabled at the GIC level anyway), - Make sure not to clear reserved SYSCIMR bits that were set before. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/soc')
-rw-r--r--drivers/soc/renesas/rcar-sysc.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index 22f0d646225c..65c8e1eb90c0 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -402,12 +402,25 @@ early_initcall(rcar_sysc_pd_init);
void __init rcar_sysc_init(phys_addr_t base, u32 syscier)
{
+ u32 syscimr;
+
if (!rcar_sysc_pd_init())
return;
rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
- /* enable all interrupt sources, but do not use interrupt handler */
+ /*
+ * Mask all interrupt sources to prevent the CPU from receiving them.
+ * Make sure not to clear reserved bits that were set before.
+ */
+ syscimr = ioread32(rcar_sysc_base + SYSCIMR);
+ syscimr |= syscier;
+ pr_debug("%s: syscimr = 0x%08x\n", __func__, syscimr);
+ iowrite32(syscimr, rcar_sysc_base + SYSCIMR);
+
+ /*
+ * SYSC needs all interrupt sources enabled to control power.
+ */
+ pr_debug("%s: syscier = 0x%08x\n", __func__, syscier);
iowrite32(syscier, rcar_sysc_base + SYSCIER);
- iowrite32(0, rcar_sysc_base + SYSCIMR);
}