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author | Douglas Anderson <dianders@chromium.org> | 2020-09-12 14:07:59 -0700 |
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committer | Mark Brown <broonie@kernel.org> | 2020-09-14 15:50:11 +0100 |
commit | fc129a43aa2705770dc45b2e9c506d2617fd5863 (patch) | |
tree | d372ab87f2b77f110b3446c98c61ca38587e60e6 /drivers/spi/spi-geni-qcom.c | |
parent | bfc430cab8234273c23885211818f704b2bd1da9 (diff) | |
download | linux-fc129a43aa2705770dc45b2e9c506d2617fd5863.tar.gz linux-fc129a43aa2705770dc45b2e9c506d2617fd5863.tar.bz2 linux-fc129a43aa2705770dc45b2e9c506d2617fd5863.zip |
spi: spi-geni-qcom: Use the FIFO even more
In commit 902481a78ee4 ("spi: spi-geni-qcom: Actually use our FIFO") I
explained that the maximum size we could program the FIFO was
"mas->tx_fifo_depth - 3" but that I chose "mas->tx_fifo_depth()"
because I was worried about decreased bandwidth.
Since that time:
* All the interconnect patches have landed, making things run at the
proper speed.
* I've done more measurements.
This lets me confirm that there's really no downside of using the FIFO
more. Specifically I did "flashrom -p ec -r /tmp/foo.bin" on a
Chromebook and averaged over several runs.
Before: It took 6.66 seconds and 59669 interrupts fired.
After: It took 6.66 seconds and 47992 interrupts fired.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200912140730.1.Ie67fa32009b94702d56232c064f1d89065ee8836@changeid
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-geni-qcom.c')
-rw-r--r-- | drivers/spi/spi-geni-qcom.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index 0dc3f4c55b0b..7f0bf0dec466 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -308,7 +308,7 @@ static int spi_geni_init(struct spi_geni_master *mas) * Hardware programming guide suggests to configure * RX FIFO RFR level to fifo_depth-2. */ - geni_se_init(se, mas->tx_fifo_depth / 2, mas->tx_fifo_depth - 2); + geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); /* Transmit an entire FIFO worth of data per IRQ */ mas->tx_wm = 1; ver = geni_se_get_qup_hw_version(se); |