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| author | Jon Lin <jon.lin@rock-chips.com> | 2022-02-16 09:40:26 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-02-17 17:15:08 +0000 |
| commit | 3a4bf922d42efa4e9a3dc803d1fd786d43e8a501 (patch) | |
| tree | 41f2f81a72d4757cdd6e339a93a06a9f9d759c9b /drivers/spi/spi-rockchip.c | |
| parent | 869f2c94db92f0f1d6acd0dff1c1ebb8160f5e29 (diff) | |
| download | linux-3a4bf922d42efa4e9a3dc803d1fd786d43e8a501.tar.gz linux-3a4bf922d42efa4e9a3dc803d1fd786d43e8a501.tar.bz2 linux-3a4bf922d42efa4e9a3dc803d1fd786d43e8a501.zip | |
spi: rockchip: Preset cs-high and clk polarity in setup progress
After power up, the cs and clock is in default status, and the cs-high
and clock polarity dts property configuration will take no effect until
the calling of rockchip_spi_config in the first transmission.
So preset them to make sure a correct voltage before the first
transmission coming.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20220216014028.8123-5-jon.lin@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-rockchip.c')
| -rw-r--r-- | drivers/spi/spi-rockchip.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 5ecd0692cca1..83da8fdb3c02 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -713,6 +713,29 @@ static bool rockchip_spi_can_dma(struct spi_controller *ctlr, return xfer->len / bytes_per_word >= rs->fifo_len; } +static int rockchip_spi_setup(struct spi_device *spi) +{ + struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller); + u32 cr0; + + pm_runtime_get_sync(rs->dev); + + cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0); + + cr0 &= ~(0x3 << CR0_SCPH_OFFSET); + cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET); + if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1) + cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET; + else if (spi->chip_select <= 1) + cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET); + + writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); + + pm_runtime_put(rs->dev); + + return 0; +} + static int rockchip_spi_probe(struct platform_device *pdev) { int ret; @@ -840,6 +863,7 @@ static int rockchip_spi_probe(struct platform_device *pdev) ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX; ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT); + ctlr->setup = rockchip_spi_setup; ctlr->set_cs = rockchip_spi_set_cs; ctlr->transfer_one = rockchip_spi_transfer_one; ctlr->max_transfer_size = rockchip_spi_max_transfer_size; |