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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-08-19 14:59:02 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-08-20 22:38:15 +0100 |
| commit | 6a195f24f3e88b9242268da79547fe4a61f30910 (patch) | |
| tree | 2755edd53841b213d7d456fbb256fb7e88355e40 /drivers/spi/spi-rspi.c | |
| parent | 4e71d926abbe9ec23415f2ec8685a7bc26c1ceed (diff) | |
| download | linux-6a195f24f3e88b9242268da79547fe4a61f30910.tar.gz linux-6a195f24f3e88b9242268da79547fe4a61f30910.tar.bz2 linux-6a195f24f3e88b9242268da79547fe4a61f30910.zip | |
spi: rspi: Increase bit rate range for QSPI
Increase bit rate range for QSPI by extending the range of supported
dividers:
1. QSPI supports a divider of 1, by setting SPBR to zero, increasing
the upper limit from 48.75 to 97.5 MHz on R-Car Gen2,
2. Make use of the Bit Rate Frequency Division Setting field in
Command Registers, to decrease the lower limit from 191 to 24 kbps
on R-Car Gen2.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200819125904.20938-6-geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-rspi.c')
| -rw-r--r-- | drivers/spi/spi-rspi.c | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index ea3f2680d3c1..38c0cd7febab 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -334,14 +334,26 @@ static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) */ static int qspi_set_config_register(struct rspi_data *rspi, int access_size) { - int spbr; + unsigned long clksrc; + int brdv = 0, spbr; /* Sets output mode, MOSI signal, and (optionally) loopback */ rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); /* Sets transfer bit rate */ - spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->speed_hz); - rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); + clksrc = clk_get_rate(rspi->clk); + if (rspi->speed_hz >= clksrc) { + spbr = 0; + } else { + spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz); + while (spbr > 255 && brdv < 3) { + brdv++; + spbr = DIV_ROUND_UP(spbr, 2); + } + spbr = clamp(spbr, 0, 255); + } + rspi_write8(rspi, spbr, RSPI_SPBR); + rspi->spcmd |= SPCMD_BRDV(brdv); /* Disable dummy transmission, set byte access */ rspi_write8(rspi, 0, RSPI_SPDCR); |